This course will be given in English.

Course number in SS 2020: L.079.05805

Due to the current situation with the Corona virus SARS-CoV-2 and the corresponding measures of Paderborn University we will run this course until further notice fully in online form. The central platform for the course is this PANDA page. We will provide all further information via PANDA, PAUL, and this website in particular about the lectures, assignments, and lab sessions. During the originally planned weekly lecture slots, i.e., Wednesdays from 13:15-14:45 and 15:00-15:45 hours and Fridays from 11:15-12:45 , we will have online lectures via ASOIC online room in IMT BigBlueButton and we discuss any open issues and answer questions. The first online lecture chat will take place on 22.04.2020 at 13:15 hours.

The course provides the most remarkable features of digital synthesis, and explains the details of transforming hardware description languages into circuit layouts. Besides, the major techniques for logic optimization are discussed, and then the efficient use of current design tools are exercised in practical sessions.

• Hardware modeling languages
• High-level synthesis and optimization methods (i.e., scheduling and binding)
• Logic Representation and optimization of two-level logic functions (exact and heuristic algorithms)
• Espresso logic minimizer
• Data structures for logic synthesis (binary decision diagrams)
• Representation and optimization of multiple-level logic networks (Algebraic methods, and Boolean methods like controllability and observability computations)
• Timing analysis and verification
• Modeling and optimization of sequential logic networks (Retiming)
• Libraries and binding
• Placement and routing algorithms

Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994.