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Team

Tim Hansmeier

Kontakt
 Tim Hansmeier

Technische Informatik

Mitglied - Wissenschaftlicher Mitarbeiter

Telefon:
+49 5251 60-4347
Büro:
O3.116
Web:
Besucher:
Pohlweg 51
33098 Paderborn

Research Interests

I work in the field of self-aware computing systems, especially in the domains of embedded and high-performance computing. Self-awareness enables a system to continuously observe and analyze its own state and the external environment to adapt accordingly and increase the system's utility. Typically, such a behavior is required if the system will face situations during operation which cannot be foreseen at design time. Hence, self-aware systems are often equipped with on-line machine learning techniques to learn on their own what actions are called for. I place my focus on the application of Learning Classifier Systems (LCS), which combine reinforcement learning with genetic algorithms to evolve a human-interpretable rule base.

If some of this sounds interesting and you think about getting involved, take a look at my list of open thesis topics below. In case there is no suitable topic announced and/or you have an own idea, feel free to contact me so we can discuss!   

Open Thesis Topics

Awards

Publications


Liste im Research Information System öffnen

Bachelorarbeiten

An FPGA Accelerator for Checking Resolution Proofs

T. Hansmeier, Bachelorarbeit, Universität Paderborn, 2017

@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }


Konferenzbeiträge

An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS

T. Hansmeier, M. Platzner, in: GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2021

@inproceedings{Hansmeier_Platzner, place={New York, NY, United States}, title={An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}, booktitle={GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Platzner, Marco} }


Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS

T. Hansmeier, in: HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), 2021

@inproceedings{Hansmeier_2021, place={New York, NY, United States}, title={Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}, DOI={10.1145/3468044.3468055}, booktitle={HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim}, year={2021} }


Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold

T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 125-126

@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}, DOI={10.1145/3377929.3389968}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={125–126} }


An Adaption Mechanism for the Error Threshold of XCSF

T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2020, pp. 1756-1764

@inproceedings{Hansmeier_Kaufmann_Platzner_2020, place={New York, NY, United States}, title={An Adaption Mechanism for the Error Threshold of XCSF}, DOI={10.1145/3377929.3398106}, booktitle={GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}, year={2020}, pages={1756–1764} }


An FPGA/HMC-Based Accelerator for Resolution Proof Checking

T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2018, pp. 153-165

Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

@inproceedings{Hansmeier_Platzner_Andrews_2018, series={Lecture Notes in Computer Science}, title={An FPGA/HMC-Based Accelerator for Resolution Proof Checking}, volume={10824}, DOI={10.1007/978-3-319-78890-6_13}, booktitle={ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco and Andrews, David}, year={2018}, pages={153–165}, collection={Lecture Notes in Computer Science} }


Zeitschriftenaufsätze

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology

T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing Systems (2019), 91(11), pp. 1259 - 1272

Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}, volume={91}, DOI={10.1007/s11265-018-1435-y}, number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019}, pages={1259–1272} }


Masterarbeiten

Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers

T. Hansmeier, Masterarbeit, Universität Paderborn, 2019

@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }


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