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Completed research projects of the High-Performance IT Systems group

The high-performance IT Systems group has been involved with numerous research projects, which are listed below. An overview of our current research projects can be found here.

SAVE – Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures

The SAVE project investigates virtualization and heterogeneous computing in high-performance and embedded computing systems. The objective is to develop a runtime system and methods for migrating workload between heterogeneous resources (multi-core CPUs, Maxeler FPGA-Systems, and GPUs) in order to achieve an optimal use of resources. Additionally we will develop virtualization methods, that allow for operating GPUs and FPGAs in virtualized environments. 

Our contribution to the project is to develop a runtime system based on a virtual machine that monitors applications during execution and analyzes their hotspots for estimating what could be gained in terms of performance and energy-efficiency when moving the workload to a different resource, e.g., from the CPU to the GPU. If the runtime system predicts that such a migration is beneficial the hotspot shall be automatically and on-the-fly extracted, optimized and compiled to the heterogeneous resource. Once the binary for the heterogeneous resource has been generated, the runtime system will migrate the execution of the hotspot from the original resource to the target resource.

Funding: European Commission, FP7 STREP Project, grant agreement 610996 
Runtime: 2013–16

EPiCS – Engineering Proprioception in Computing Systems

EPiCS was a trans-national multi-disciplinary research project, which aimed at laying the foundation for engineering proprioceptive computing systems. Such systems collect and maintain information about their state and progress and reason about their behavior. This self-awareness allows the systems to autonomously adapt their behavior to changing conditions (self-expression). The concepts of self-awareness and self-expression are new to the domains of computing and networking; the successful transfer and development of these concepts will help create future heterogeneous and distributed systems capable of efficiently responding to a multitude of requirements with respect to functionality and flexibility, performance, resource usage and costs, reliability and safety, and security.

Our contribution to the EPiCS project was to study the architecture and operating systems for heterogeneous multi-core systems that are composed of CPUs, fixed function accelerators and reconfigurable accelerators. These heterogeneous multi-core systems allow for optimizing their behavior by migrating functionality between the heterogeneous computing resources for optimizing performance and efficiency goals.

Funding: European Commission, FP7 FET Integrated Project, grant agreement 257906
Runtime: 2010–14

ENHANCE – Enabling Heterogeneous Hardware Acceleration Using Novel Programming and Scheduling Models

ENHANCE was a research project carried out by German academic and industrial partners. The project aimed at a better integration and simplified usage of heterogeneous computing resources in high-performance computing systems. Heterogeneous computing systems contain multiple compute components, for example, multi-core processors, graphics processing units (GPUs), or field programmable gate arrays (FPGAs). While the use of compute accelerators promises significant improvements in performance and energy efficiency, developing applications for such heterogeneous systems raises challenges in programmability, performance estimation and scheduling. The ENHANCE project addressed these challenges by providing a compilation framework for porting applications to compute accelerators and a runtime system for scheduling tasks on heterogeneous resources.

Our contribution to the ENHANCE project was to develop a novel runtime system, that allows for time sharing and load-balancing of tasks, when executed on heterogeneous resources. To this end, we developed a new programming model that uses architecture independent checkpoints to allow migrating code between different compute resources. Further, we developed an extension to the Linux completely fair scheduler to allow for time-sharing of arbitrary compute resources and for migrating workload among compute resources to achieve a user defined objective, e.g., maximizing throughput, minimizing the average turn-around time, or maximizing energy efficiency.

Funding: German Federal Ministry of Education and Research (BMBF), grant agreement 01|H11004
Runtime: 2011–13

Custom Computing Architectures for Nanophotonics

In this project we studied, how modern parallel and reconfigurable computer architectures, in particular FPGAs and GPUs, can be used effectively for simulations in theoretical physics. The target algorithm we studied is Yee's Finite-Difference Time Domain method for solving Maxwell's equations. This project that was initially funded by the Paderborn University Research Award, which was jointly awarded to Prof. Plessl and Prof. Förstner in 2009, was the basis for a longstanding collaboration with Prof. Förstner.

Initial funding: Paderborn University Research Award (2009)
Runtime: 2009–11

MM-RPU – A Multimode Reconfigurable Processing Unit

The project A Multimode Reconfigurable Processing Unit (initially funded by the Intel Microprocessor Technology Lab) studied how reconfigurable processing units can be integrated in microprocessors while maintaining a software-centric programming model. We have developed a high-level performance estimation framework that combines an analytic performance model (characterizing the hardware latencies, bandwidth, execution times) with application-specific data determined by static program analysis and traces generated by executing instrumented code. Using this framework we could perform a design space exploration for determining the optimal architecture for a given set of benchmark applications. Additionally, we could analyze the sensitivity of the results with respect to the parameters of the hardware architecture, e. g., communication bandwidth between CPU and reconfigurable processing unit.

Initial funding: Intel Microprocessor Technology Lab
Runtime: 2008–12

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