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Current research projects of the High-Performance IT Systems group

The high-performance IT Systems group has been involved with numerous research projects. Many of our projects are funded by third research funding agencies such as: the Germany Research Foundation (DFG), Germany Ministry for Education and Research (BMBF), the European Commission. An overview of our completed research projects can be found here.

Below is a list of our ongoing research projects.

HighPerMeshes – Domain-specific programming and target architecture aware compiler infrastructure for algorithms on unstructured grids

The goal of the project HighPerMeshes is to develop a practically usable domain-specific framework for the efficient, parallel and scaling implementation of iterative algorithms on unstructured grids. Simulation software in the time domain, that falls into this category (e.g. TD-FEM, TD-DG, network simulations), has increasingly been used in scientific and industrial domains in recent years and complements or supplements comparable methods on structured grids. With the results of this project, developers can with moderate effort extend existing source codes in high-level languages by domain-specific library and language elements. The intelligent compiler infrastructure uses domain knowledge to enable performance optimized, highly parallel execution on all relevant modern hardware architectures (Multicore, Manycore, GPU, FPGA), also in heterogeneous systems. Thus, the project offers to many HPC developers from science and industry an easy and sustainable path towards scaling usage of the most efficient current and future target architectures.

Paderborn University is the project consortium manager and involved in all work packages. The focus under the lead of Prof. Dr. Christian Plessl (High-Performance IT Systems) are the optimization and code generation for FPGAs as target platform, as well as the integration of communication end points on FPGAs. The main activity under the lead of Prof. Dr. Jens Förstner (Theoretical Electrical Engineering) are the requirement analysis and co-design from the nanophotonics perspective and the evaluation in this domain. Embedding the project into PC2 provides furthermore HPC-infrastructure, and additionally broad expertise and dissemination potential in scientific computing.

Funding: German Ministry for Education and Research, 01|H16005A
Program: 5th HPC Software Call
Runtime: 04/2017–03/2019
Website: TBA

PerficienCC - Performance and Efficiency in HPC with Custom Computing

To improve the energy efficiency of HPC systems they are increasingly augmented with hardware accelerators. The use of accelerators does however fall behind their fundamental performance and efficiency potential. In the PerficienCC project we work at closing this gap in cooperation with computational scientists that are customers of the HPC services at the Paderborn Center for Parallel Computing. We focus on application-specific hardware accelerators based on FPGAs. Through a tight cooperation of FPGA experts in our research group and developers of scientific codes at Paderborn University we will study the potential to accelerate important applications with FPGAs and we will port open-source scientific software to FPGAs. Additionally, we will provide generalized code with FPGA support as libraries to the community and will generate training material to educate computational scientists in this area. Our project aims at making FPGA technology more accessible and providing an empirical evaluation of the benefit of FPGAs for HPC and data center applications.

Funding: Germany Science Foundation
Program: Performance Engineering für wissenschaftliche Software
Runtime: 6/2017 (planned) - 5/2020

On-the-Fly Hardware Acceleration – subproject of the Collaborative Research Center 901 'On-the-Fly Computing'

The objective of CRC 901 – On-The-Fly Computing (OTF Computing) – is to develop techniques and processes for automatic on-the-fly configuration and provision of individual IT services out of base services that are available on world-wide markets. In addition to the configuration by special OTF service providers and the provision by what are called OTF Compute Centers, this involves developing methods for quality assurance and the protection of participating clients and providers, methods for the target-oriented further development of markets, and methods to support the interaction of the participants in dynamically changing markets.

Our contribution to the CRC 901 is to study whether on-the-fly compute centers that execute configured and composed IT services can optimize the execution by leveraging accelerators based on reconfigurable hardware. We assume that composed services will only be available as binaries, hence the process of offloading computations to hardware accelerators must operate on binary applications and needs to be completely transparent to the user. Our objective is to analyze, whether such a transparent optimization is feasible and if so, to determine the potential as well as the limitations of this approach.

Funding: German Science Foundation (DFG), collaborative research center SFB 901
Runtime: since 2012

Further information:

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