Conference papers

Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL

M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.

DOI

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

A.R. Tareen, M. Meyer, C. Plessl, T. Kenter, in: 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2024.

DOI

Optimisation and Evaluation of Breadth First Search with oneAPI/SYCL on Intel FPGAs: from Describing Algorithms to Describing Architectures

K. Olgu, T. Kenter, J. Nunez-Yanez, S. Mcintosh-Smith, in: Proceedings of the 12th International Workshop on OpenCL and SYCL, ACM, 2024.

DOI

SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry using HBM-based FPGAs

P. Stachura, G. Li, X. Wu, C. Plessl, Z. Fang, in: 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024, pp. 60–68.

DOI

StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs

J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.

DOI

A computation of D(9) using FPGA Supercomputing

L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ArXiv:2304.03039 (2023).

arXiv

Computing and Compressing Electron Repulsion Integrals on FPGAs

X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173.

DOI arXiv

FPGA Acceleration for HPC Supercapacitor Simulations

C. Prouveur, M. Haefele, T. Kenter, N. Voss, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2023.

DOI Open Access available via this link.

Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation

J.-O. Opdenhövel, C. Plessl, T. Kenter, in: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), ACM, 2023.

DOI

Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes

J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2023.

DOI Open Access available via this link.

A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges

M. Karp, A. Podobas, T. Kenter, N. Jansson, C. Plessl, P. Schlatter, S. Markidis, in: International Conference on High Performance Computing in Asia-Pacific Region, ACM, 2022.

DOI

CP2K on the road to exascale

T. Kühne, C. Plessl, R. Schade, O. Schütt, ArXiv:2205.14741 (2022).

arXiv

Roadmap on Electronic Structure Codes in the Exascale Era

V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022).

arXiv

Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA

T. Kenter, A. Shambhu, S. Faghih-Naini, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2021.

DOI Open Access available via this link.

High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection

M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.

DOI

High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection

M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.

DOI

A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K

M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.

DOI arXiv

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite

M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.

DOI Official repository of the benchmark suite on GitHub

OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs

P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.

DOI

A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices

M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.

DOI arXiv

Automated Code Acceleration Targeting Heterogeneous OpenCL Devices

H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.

DOI

OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes

T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.

DOI

Flexible FPGA design for FDTD using OpenCL

T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.

DOI

Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension

M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.

DOI

Microdisk Cavity FDTD Simulation on FPGA using OpenCL

T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.

Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)

T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center

A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.

Using Approximate Computing in Scientific Codes

M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.

Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems

H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.

Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems

H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.

DOI

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores

M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.

PDF arXiv

How Do They Find Their Place? A Longitudinal Study of Management Students' Attitudes and Motivations During Their First Year at Business School

T. Jenert, T. Brahm, in: 2015.

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm

J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.

DOI

Transparent offloading of computational hotspots from binary code to Xeon Phi

M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.

DOI

Deferring Accelerator Offloading Decisions to Application Runtime

G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

DOI

Kernel-Centric Acceleration of High Accuracy Stereo-Matching

T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

DOI

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer

T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.

DOI

Reconstructing AES Key Schedules from Decayed Memory with FPGAs

H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.

DOI

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach

G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.

DOI

SAVE: Towards efficient resource management in heterogeneous system architectures

G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.

DOI

FPGA-accelerated Key Search for Cold-Boot Attacks against AES

H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.

DOI

On-The-Fly Computing: A Novel Paradigm for Individualized IT Services

M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.

DOI

Parallel Macro Pipelining on the Intel SCC Many-Core Computer

T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.

DOI

A Data Driven Science Gateway for Computational Workflows

R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.

Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?

B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.

DOI

Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators

M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.

DOI

Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs

C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.

DOI

Hardware/Software Platform for Self-aware Compute Nodes

M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.

Pragma based parallelization - Trading hardware efficiency for ease of use?

T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.

DOI

Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux

T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.

Turning control flow graphs into function calls: Code generation for heterogeneous architectures

P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.

DOI

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler

T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.

DOI

Estimation and Partitioning for CPU-Accelerator Architectures

T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.

Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture

M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.

DOI

Measuring and Predicting Temperature Distributions on FPGAs at Run-Time

M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.

DOI

Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures

T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.

DOI

Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend

B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.

DOI

An Open Source Circuit Library with Benchmarking Facilities

M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.

Configurable Processor Architectures: History and Trends

D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.

Performance Estimation for the Exploration of CPU-Accelerator Architectures

T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: O. Hammami, S. Larrabee (Eds.), Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA), 2010.

Pruning the Design Space for Just-In-Time Processor Customization

M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.

DOI

Reconfigurable Nodes for Future Networks

A. Keller, B. Plattner, E. Lübbers, M. Platzner, C. Plessl, in: Proc. IEEE Globecom Workshop on Network of the Future (FutureNet), IEEE, 2010, pp. 372–376.

DOI

Rupeas: Ruby Powered Event Analysis DSL

M. Woehrle, C. Plessl, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, 2010, pp. 245–248.

DOI

Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware

E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.

Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators

T. Beisel, M. Niekamp, C. Plessl, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2010, pp. 65–72.

DOI

An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure

T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344.

Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000

T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.

DOI

EvoCaches: Application-specific Adaptation of Cache Mapping

P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.

IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing

T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.

DOI

PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes

J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.

Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX

M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.

A Hardware Accelerator for k-th Nearest Neighbor Thinning

T. Schumacher, R. Meiche, P. Kaufmann, E. Lübbers, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.

EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks

M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer Society, Los Alamitos, CA, USA, 2008, pp. 201–208.

DOI

IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers

T. Schumacher, C. Plessl, M. Platzner, in: Many-Core and Reconfigurable Supercomputing Conference (MRSC), 2008.

Automated Wireless Sensor Network Testing

J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele, in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA, 2007, pp. 303–303.

DOI

Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework

M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, New York, NY, USA, 2007, pp. 93–97.

DOI

Optimal Temporal Partitioning based on Slowdown and Retiming

C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.

DOI

Zippy – A coarse-grained reconfigurable array with support for hardware virtualization

C. Plessl, M. Platzner, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2005, pp. 213–218.

DOI

Virtualization of Hardware – Introduction and Survey

C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2004, pp. 63–69.

Co-simulation of a Hybrid Multi-Context Architecture

R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot

C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2003, pp. 252–259.

DOI

Virtualizing Hardware with Multi-Context Reconfigurable Arrays

R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2003, pp. 151–160.

DOI

Custom Computing Machines for the Set Covering Problem

C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2002, pp. 163–172.

DOI

Partially Reconfigurable Cores for Xilinx Virtex

M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), Springer, 2002, pp. 292–301.

DOI

Reconfigurable Hardware in Wearable Computing Nodes

C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, in: Proc. Int. Symp. on Wearable Computers (ISWC), IEEE Computer Society, 2002, pp. 215–222.

DOI

Instance-Specific Accelerators for Minimum Covering

C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.

Reconfigurable Processors for Handhelds and Wearables: Application Analysis

R. Enzler, M. Platzner, C. Plessl, L. Thiele, G. Tröster, in: Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, 2001, pp. 135–146.

DOI

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