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Technische Informatik

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Journal papers

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RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures

F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro (2022), 42(6), pp. 125-133

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DOI

Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.

@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={10.1109/MM.2022.3202091}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }

Software/Hardware Co-Verification for Custom Instruction Set Processors

M. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021)

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Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.

@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs

A. Rodriguez, A. Otero, M. Platzner, E. De la Torre, IEEE Transactions on Computers (2021), pp. 1-1

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@article{Rodriguez_Otero_Platzner_De la Torre_2021, title={Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs}, DOI={10.1109/tc.2021.3107196}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rodriguez, Alfonso and Otero, Andres and Platzner, Marco and De la Torre, Eduardo}, year={2021}, pages={1–1} }

Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis

A. Boschmann, D. Neuhaus, S. Vogt, C. Kaltschmidt, M. Platzner, S. Dosen, Journal of NeuroEngineering and Rehabilitation (2021), 18(1), 25

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<jats:title>Abstract</jats:title><jats:sec> <jats:title>Background</jats:title> <jats:p>Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training.</jats:p> </jats:sec><jats:sec> <jats:title>Methods</jats:title> <jats:p>In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback.</jats:p> </jats:sec><jats:sec> <jats:title>Results</jats:title> <jats:p>The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7).</jats:p> </jats:sec><jats:sec> <jats:title>Conclusion</jats:title> <jats:p>The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development.</jats:p> </jats:sec>

@article{Boschmann_Neuhaus_Vogt_Kaltschmidt_Platzner_Dosen_2021, title={Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis}, volume={18}, DOI={10.1186/s12984-021-00822-6}, number={125}, journal={Journal of NeuroEngineering and Rehabilitation}, publisher={Springer Science and Business Media LLC}, author={Boschmann, Alexander and Neuhaus, Dorothee and Vogt, Sarah and Kaltschmidt, Christian and Platzner, Marco and Dosen, Strahinja}, year={2021} }

Design of Distributed Reconfigurable Robotics Systems with ReconROS

C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (2021), pp. 1-20

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Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.

@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, DOI={10.1145/3494571}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen, Christian and Platzner, Marco}, year={2021}, pages={1–20} }

Proof-carrying Approximate Circuits

L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems (2020), 28(9), pp. 2084 - 2088

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Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.

@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }

Evolution of Application-Specific Cache Mappings

N. Ho, P. Kaufmann, M. Platzner, International Journal of Hybrid intelligent Systems (2020)

Zitation (Bibtex)

@article{Ho_Kaufmann_Platzner_2020, title={Evolution of Application-Specific Cache Mappings}, journal={International Journal of Hybrid intelligent Systems}, publisher={IOS Press}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2020} }

Dynamic Reliability Management for FPGA-Based Systems

J. Anwer, S. Meisner, M. Platzner, International Journal of Reconfigurable Computing (2020), pp. 1-19

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<jats:p>Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.</jats:p>

@article{Anwer_Meisner_Platzner_2020, title={Dynamic Reliability Management for FPGA-Based Systems}, DOI={10.1155/2020/2808710}, journal={International Journal of Reconfigurable Computing}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2020}, pages={1–19} }

Self-aware Cyber-Physical Systems

K. Bellman, N. Dutt, L. Esterle, A. Herkersdorf, A. Jantsch, C. Landauer, P. R. Lewis, M. Platzner, N. TaheriNejad, K. Tammemäe, ACM Transactions on Cyber-Physical Systems (2020), Accepted for Publication, pp. 1-24

Zitation (Bibtex)

@article{Bellman_Dutt_Esterle_Herkersdorf_Jantsch_Landauer_R. Lewis_Platzner_TaheriNejad_Tammemäe_2020, title={Self-aware Cyber-Physical Systems}, volume={Accepted for Publication}, journal={ACM Transactions on Cyber-Physical Systems}, author={Bellman, K. and Dutt, N. and Esterle, L. and Herkersdorf, A. and Jantsch, A. and Landauer, C. and R. Lewis, P. and Platzner, Marco and TaheriNejad, N. and Tammemäe, K.}, year={2020}, pages={1–24} }

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation

L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability (2019), 99, pp. 277-290

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Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.

@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology

T. Hansmeier, M. Platzner, M.J.H. Pantho, D. Andrews, Journal of Signal Processing Systems (2019), 91(11), pp. 1259 - 1272

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Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

@article{Hansmeier_Platzner_Pantho_Andrews_2019, title={An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}, volume={91}, DOI={10.1007/s11265-018-1435-y}, number={11}, journal={Journal of Signal Processing Systems}, author={Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}, year={2019}, pages={1259–1272} }

FPGAs im Rechenzentrum

M. Platzner, C. Plessl, Informatik Spektrum (2019)

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@article{Platzner_Plessl_2019, title={FPGAs im Rechenzentrum}, DOI={10.1007/s00287-019-01187-w}, journal={Informatik Spektrum}, author={Platzner, Marco and Plessl, Christian}, year={2019} }

plessl19_informatik_spektrum.pdf -

Zynq-based acceleration of robust high density myoelectric signal processing

A. Boschmann, A. Agne, G. Thombansen, L.M. Witschen, F. Kraus, M. Platzner, Journal of Parallel and Distributed Computing (2019), 123, pp. 77-89

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Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels.

@article{Boschmann_Agne_Thombansen_Witschen_Kraus_Platzner_2019, title={Zynq-based acceleration of robust high density myoelectric signal processing}, volume={123}, DOI={10.1016/j.jpdc.2018.07.004}, journal={Journal of Parallel and Distributed Computing}, publisher={Elsevier}, author={Boschmann, Alexander and Agne, Andreas and Thombansen, Georg and Witschen, Linus Matthias and Kraus, Florian and Platzner, Marco}, year={2019}, pages={77–89} }

R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints

I. Ghribi, R.B. Abdallah, M. Khalgui, Z. Li, K. Alnowibet, M. Platzner, IEEE Access (2018), pp. 14078-14092

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@article{Ghribi_Abdallah_Khalgui_Li_Alnowibet_Platzner_2018, title={R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints}, DOI={10.1109/access.2018.2799852}, journal={IEEE Access}, author={Ghribi, Ines and Abdallah, Riadh Ben and Khalgui, Mohamed and Li, Zhiwu and Alnowibet, Khalid and Platzner, Marco}, year={2018}, pages={14078–14092} }

Proof-Carrying Hardware via Inductive Invariants

T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017)(4), pp. 61:1--61:23

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Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.

@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={10.1145/3054743}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }

Fast Network Restoration by Partitioning of Parallel Black Start Zones

C. Shen, P. Kaufmann, M. Braun, The Journal of Engineering (2017), pp. 19pp

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@article{Shen_Kaufmann_Braun_2017, title={Fast Network Restoration by Partitioning of Parallel Black Start Zones}, DOI={10.1049/joe.2017.0032}, journal={The Journal of Engineering}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={19pp} }

Three-Stage Power System Restoration Methodology Considering Renewable Energies

C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) (2017)

Zitation (Bibtex)

@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017} }

The First 25 Years of the FPL Conference – Significant Papers

P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, ACM Transactions on Reconfigurable Technology and Systems (2017)

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@article{H.W. Leong_Amano_Anderson_Bertels_M.P. Cardoso_Diessel_Gogniat_Hutton_Lee_Luk_et al._2017, title={The First 25 Years of the FPL Conference – Significant Papers}, DOI={10.1145/2996468}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~{a}o and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and et al.}, year={2017} }

Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)

R. F. DeMara, M. Platzner, M. Ottavi, IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing (2017)

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@article{F. DeMara_Platzner_Ottavi_2017, title={Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial)}, DOI={10.1109/TETC.2016.2641599}, journal={IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing}, author={F. DeMara, Ronald and Platzner, Marco and Ottavi, Marco}, year={2017} }

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus

J. Anwer, M. Platzner, Microprocessors and Microsystems (2017), pp. 160-172

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@article{Anwer_Platzner_2017, title={Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus}, DOI={10.1016/j.micpro.2017.06.002}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2017}, pages={160–172} }

Three-Stage Power System Restoration Methodology Considering Renewable Energies

C. Shen, P. Kaufmann, M. Braun, Elsevier International Journal of Electrical Power and Energy Systems (IJEPES) (2017), 94, pp. 287-299

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This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.

@article{Shen_Kaufmann_Braun_2017, title={Three-Stage Power System Restoration Methodology Considering Renewable Energies}, volume={94}, DOI={10.1016/j.ijepes.2017.07.007}, journal={Elsevier International Journal of Electrical Power and Energy Systems (IJEPES)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2017}, pages={287–299} }

An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip

T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering (2016), pp. 112--122

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Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={10.1016/j.compeleceng.2016.04.005}, journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }

Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control

C. Ma, P. Kaufmann, J. Töbermann, M. Braun, Renewable Energy (2016), 87((part 2)), pp. 946-953

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@article{Ma_Kaufmann_Töbermann_Braun_2016, title={Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control}, volume={87}, DOI={10.1016/j.renene.2015.07.083}, number={(part 2)}, journal={Renewable Energy}, publisher={Elsevier}, author={Ma, Chenjie and Kaufmann, Paul and Töbermann, J.-Christian and Braun, Martin}, year={2016}, pages={946–953} }

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation

H. Ghasemzadeh Mohammadi, P. Gaillardon, G. De Micheli, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2016), PP(99), pp. 1-1

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@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908}, number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1} }

Adaptive playouts for online learning of policies during Monte Carlo Tree Search

T. Graf, M. Platzner, Journal Theoretical Computer Science (2016), 644, pp. 53-62

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@article{Graf_Platzner_2016, title={Adaptive playouts for online learning of policies during Monte Carlo Tree Search}, volume={644}, DOI={10.1016/j.tcs.2016.06.029}, journal={Journal Theoretical Computer Science}, publisher={Elsevier}, author={Graf, Tobias and Platzner, Marco}, year={2016}, pages={53–62} }

Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study

T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) (2015), 2015, 859425

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FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }

Self-Aware and Self-Expressive Systems – Guest Editor's Introduction

J. Torresen, C. Plessl, X. Yao, IEEE Computer (2015), 48(7), pp. 18-20

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@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }

Aktuelles Schlagwort: Approximate Computing

C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015)(5), pp. 396-399

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DOI

@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

H. Ghasemzadeh Mohammadi, P. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology (2015), 14(6), pp. 1117-1126

Zitation (Bibtex)

DOI

@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores

A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) (2014), 7(2), 13

Zitation (Bibtex)

DOI

Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.

@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators

A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems (2014), 38(8, Part B), pp. 911-919

Zitation (Bibtex)

DOI

Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.

@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }

ReconOS - An Operating System Approach for Reconfigurable Computing

A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro (2014), 34(1), pp. 60-71

Zitation (Bibtex)

DOI

The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications

@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers

H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News (2014), 41(5), pp. 65-70

Zitation (Bibtex)

DOI

@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }

A Novel Technique and its Application to Computer Go

L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games (2014), 6(3), pp. 361-374

Zitation (Bibtex)

DOI

@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={10.1109/TCIAIG.2014.2346997}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }

An FPGA-based Reconfigurable Mesh Many-Core

H. Giefers, M. Platzner, IEEE Transactions on Computers (2014), 63(12), pp. 2919 - 2932

Zitation (Bibtex)

DOI

@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={10.1109/TC.2013.174}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }

Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices

S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems (2013), 22(3), pp. 522-536

Zitation (Bibtex)

DOI

@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }

Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers

P. Kaufmann, K. Glette, T. Gruber, M. Platzner, J. Torresen, B. Sick, IEEE Transactions on Evolutionary Computation (2013), 17(1), pp. 46-63

Zitation (Bibtex)

DOI

@article{Kaufmann_Glette_Gruber_Platzner_Torresen_Sick_2013, title={Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers}, volume={17}, DOI={10.1109/TEVC.2012.2185845}, number={1}, journal={IEEE Transactions on Evolutionary Computation}, author={Kaufmann, Paul and Glette, Kyrre and Gruber, Tiemo and Platzner, Marco and Torresen, Jim and Sick, Bernhard}, year={2013}, pages={46–63} }

A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking

M. Happe, E. Lübbers, M. Platzner, International Journal of Real-time Image Processing (2013), 8(1), pp. 95 - 110

Zitation (Bibtex)

DOI

@article{Happe_Lübbers_Platzner_2013, title={A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking}, volume={8}, DOI={doi:10.1007/s11554-011-0212-y}, number={1}, journal={International Journal of Real-time Image Processing}, publisher={Springer}, author={Happe, Markus and Lübbers, Enno and Platzner, Marco}, year={2013}, pages={95–110} }

On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors

M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012)

Zitation (Bibtex)

DOI

@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }

STIR: Software for Tomographic Image Reconstruction Release 2

K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology (2012), 57(4), pp. 867-883

Zitation (Bibtex)

DOI

@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }

Parallel algorithm for computation of second-order sequential best rotations

S. Redif, S. Kasap, Int. Journal of Electronics (2012), 100(12), pp. 1646-1651

Zitation (Bibtex)

DOI

@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }

Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer

S. Kasap, K. Benkrid, Journal of Computers (2012), 7(6), pp. 1312-1328

Zitation (Bibtex)

@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }

IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators

T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems (2012), 36(2), pp. 110-126

Zitation (Bibtex)

DOI

@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }

Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture

P. Kaufmann, K. Glette, M. Platzner, J. Torresen, International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) (2012), 3(4), pp. 17-31

Zitation (Bibtex)

DOI

@article{Kaufmann_Glette_Platzner_Torresen_2012, title={Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture}, volume={3}, DOI={10.4018/jaras.2012100102}, number={4}, journal={International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)}, publisher={IGI Global}, author={Kaufmann, Paul and Glette, Kyrre and Platzner, Marco and Torresen, Jim}, year={2012}, pages={17–31} }

FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study

T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- figurable Computing (IJRC) (2011)

Zitation (Bibtex)

DOI

@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={10.1155/2011/760954}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }

Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)

U. Kebschull, M. Platzner, J. Teich, IET Computers Digital Techniques (2010), 4(3), pp. 157-158

Zitation (Bibtex)

DOI

@article{Kebschull_Platzner_Teich_2010, title={Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial)}, volume={4}, DOI={10.1049/iet-cdt.2010.9044}, number={3}, journal={IET Computers Digital Techniques}, author={Kebschull, Udo and Platzner, Marco and Teich, Jürgen}, year={2010}, pages={157–158} }

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

S. Drzevitzky, U. Kastens, M. Platzner, International Journal of Reconfigurable Computing (2010), 2010

Zitation (Bibtex)

DOI

@article{Drzevitzky_Kastens_Platzner_2010, title={Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification}, volume={2010}, DOI={10.1155/2010/180242}, journal={International Journal of Reconfigurable Computing}, publisher={Hindawi Publishing Corporation}, author={Drzevitzky, Stephanie and Kastens, Uwe and Platzner, Marco}, year={2010} }

ReconOS: Multithreaded Programming for Reconfigurable Computers

E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems (2009), 9(1), pp. 8:1-8:33

Zitation (Bibtex)

DOI

@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={10.1145/1596532.1596540}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }

Server-based execution of periodic tasks on dynamically reconfigurable hardware

K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques (2007), 1(4), pp. 295-302

Zitation (Bibtex)

DOI

@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={10.1049/iet-cdt:20060186}, number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }

Dynamically Reconfigurable Architectures (editorial)

N. Bergmann, M. Platzner, J. Teich, {EURASIP} Journal on Embedded Systems (2007), 2007, pp. 1-2

Zitation (Bibtex)

DOI

@article{Bergmann_Platzner_Teich_2007, title={Dynamically Reconfigurable Architectures (editorial)}, volume={2007}, DOI={10.1155/2007/28405}, journal={{EURASIP} Journal on Embedded Systems}, publisher={Springer Science+Business Media}, author={Bergmann, Neil and Platzner, Marco and Teich, Jürgen}, year={2007}, pages={1–2} }

System-level performance evaluation of reconfigurable processors

R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems (2005), 29(2-3), pp. 63-73

Zitation (Bibtex)

DOI

Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.

@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }

Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks

C. Steiger, H. Walder, M. Platzner, {IEEE} Transactions on Computers (2004), 53(11), pp. 1393-1407

Zitation (Bibtex)

DOI

@article{Steiger_Walder_Platzner_2004, title={Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks}, volume={53}, DOI={10.1109/tc.2004.99}, number={11}, journal={{IEEE} Transactions on Computers}, author={Steiger, Christoph and Walder, Herbert and Platzner, Marco}, year={2004}, pages={1393–1407} }

Instance-Specific Accelerators for Minimum Covering

C. Plessl, M. Platzner, Journal of Supercomputing (2003), 26(2), pp. 109-129

Zitation (Bibtex)

DOI

This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.

@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }

The Case for Reconfigurable Hardware in Wearable Computing

C. Plessl, R. Enzler, H. Walder, J. Beutel, M. Platzner, L. Thiele, G. Tröster, Personal and Ubiquitous Computing (2003), 7(5), pp. 299-308

Zitation (Bibtex)

DOI

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

@article{Plessl_Enzler_Walder_Beutel_Platzner_Thiele_Tröster_2003, title={The Case for Reconfigurable Hardware in Wearable Computing}, volume={7}, DOI={10.1007/s00779-003-0243-x}, number={5}, journal={Personal and Ubiquitous Computing}, publisher={Springer}, author={Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}, year={2003}, pages={299–308} }

A Framework for Run-time Reconfigurable Systems

M. Eisenring, M. Platzner, The Journal of Supercomputing (2002), 21(2), pp. 145-159

Zitation (Bibtex)

DOI

@article{Eisenring_Platzner_2002, title={A Framework for Run-time Reconfigurable Systems}, volume={21}, DOI={10.1023/a:1013627403946}, number={2}, journal={The Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Eisenring, Michael and Platzner, Marco}, year={2002}, pages={145–159} }

Object-oriented domain specific compilers for programming FPGAs

O. Mencer, M. Platzner, M. Morf, M. J. Flynn, {IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems (2001), 9(1), pp. 205-210

Zitation (Bibtex)

DOI

@article{Mencer_Platzner_Morf_J. Flynn_2001, title={Object-oriented domain specific compilers for programming FPGAs}, volume={9}, DOI={10.1109/92.920835}, number={1}, journal={{IEEE} Transactions on Very Large Scale Integration ({VLSI}) Systems}, author={Mencer, Oskar and Platzner, Marco and Morf, Martin and J. Flynn, Michael}, year={2001}, pages={205–210} }

Reconfigurable accelerators for combinatorial problems

M. Platzner, Computer (2000), 33(4), pp. 58-60

Zitation (Bibtex)

DOI

@article{Platzner_2000, title={Reconfigurable accelerators for combinatorial problems}, volume={33}, DOI={10.1109/2.839322}, number={4}, journal={Computer}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Platzner, Marco}, year={2000}, pages={58–60} }

Toward embedded qualitative simulation: a specialized computer architecture for QSim

M. Platzner, B. Rinner, R. Weiss, IEEE Intelligent Systems (2000), 15(2), pp. 62-68

Zitation (Bibtex)

DOI

@article{Platzner_Rinner_Weiss_2000, title={Toward embedded qualitative simulation: a specialized computer architecture for QSim}, volume={15}, DOI={10.1109/5254.850829}, number={2}, journal={IEEE Intelligent Systems}, publisher={Institute of Electrical {\&} Electronics Engineers ({IEEE})}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={2000}, pages={62–68} }

Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems

M. Eisenring, M. Platzner, IEE Proceedings -- Computers & Digital Techniques (2000), 147, pp. 159-165

Zitation (Bibtex)

DOI

@article{Eisenring_Platzner_2000, title={Synthesis of Interfaces and Communication in Reconfigurable Embedded Systems}, volume={147}, DOI={10.1049/ip-cdt:20000496}, journal={IEE Proceedings -- Computers & Digital Techniques}, publisher={IET}, author={Eisenring, Michael and Platzner, Marco}, year={2000}, pages={159–165} }

Reconfigurable Computer Architectures

M. Platzner, e&i Elektrotechnik und Informationstechnik (1998), 115, pp. 143-148

Zitation (Bibtex)

@article{Platzner_1998, title={Reconfigurable Computer Architectures}, volume={115}, journal={e&i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco}, year={1998}, pages={143–148} }

Design and Implementation of a Parallel Constraint Satisfaction Algorithm

M. Platzner, B. Rinner, International Journal of Computers & Their Applications (1998), 5, pp. 106-116

Zitation (Bibtex)

@article{Platzner_Rinner_1998, title={Design and Implementation of a Parallel Constraint Satisfaction Algorithm}, volume={5}, journal={International Journal of Computers & Their Applications}, publisher={ISCA}, author={Platzner, Marco and Rinner, Bernhard}, year={1998}, pages={106–116} }

Parallel qualitative simulation

M. Platzner, B. Rinner, R. Weiss, Simulation Practice and Theory (1997), 5(7-8), pp. 623-638

Zitation (Bibtex)

DOI

@article{Platzner_Rinner_Weiss_1997, title={Parallel qualitative simulation}, volume={5}, DOI={10.1016/s0928-4869(97)00008-6}, number={7–8}, journal={Simulation Practice and Theory}, publisher={Elsevier}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={623–638} }

A Computer Architecture to Support Qualitative Simulation in Industrial Applications

M. Platzner, B. Rinner, R. Weiss, e & i Elektrotechnik und Informationstechnik (1997), 114, pp. 13-18

Zitation (Bibtex)

@article{Platzner_Rinner_Weiss_1997, title={A Computer Architecture to Support Qualitative Simulation in Industrial Applications}, volume={114}, journal={e & i Elektrotechnik und Informationstechnik}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1997}, pages={13–18} }

Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation

M. Platzner, B. Rinner, R. Weiss, J.UCS Journal of Universal Computer Science (1995), 12, pp. 811-820

Zitation (Bibtex)

@article{Platzner_Rinner_Weiss_1995, title={Exploiting Parallelism in Constraint Satisfaction for Qualitative Simulation}, volume={12}, journal={J.UCS Journal of Universal Computer Science}, publisher={Springer}, author={Platzner, Marco and Rinner, Bernhard and Weiss, Reinhold}, year={1995}, pages={811–820} }

Erfahrungen mit einer Multi-Signalprozessorarchitektur (TMS320C40)

M. Platzner, C. Steger, Mikroelektronik (1993)

Zitation (Bibtex)

@article{Platzner_Steger_1993, title={Erfahrungen mit einer Multi-Signalprozessorarchitektur (TMS320C40)}, journal={Mikroelektronik}, author={Platzner, Marco and Steger, Christian}, year={1993} }

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