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Teaching

Completed Thesis Projects

Bachelor's Theses


Liste im Research Information System öffnen

An Evaluation of XCS on the OpenAI Gym

F. Mehlich, Bachelorarbeit, Paderborn University, 2022

@book{Mehlich_2022, place={Paderborn}, title={An Evaluation of XCS on the OpenAI Gym}, publisher={Paderborn University}, author={Mehlich, Florian}, year={2022} }


Implementation and Profiling of XCS in the Context of Embedded Systems

M. Brede, Bachelorarbeit, Paderborn University, 2021

This bachelor thesis presents a C/C++ implementation of the XCS algorithm for an embedded system and profiling results concerning the execution time of the functions. These are then analyzed in relation to the input characteristics of the examined learning environments and compared with related work. Three main conclusions can be drawn from the measured results. First, the maximum size of the population of the classifiers influences the runtime of the genetic algorithm; second, the size of the input space has a direct effect on the execution time of the matching function; and last, a larger action space results in a longer runtime generating the prediction for the possible actions. The dependencies identified here can serve to optimize the computational efficiency and make XCS more suitable for embedded systems.

@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling of XCS in the Context of Embedded Systems}, publisher={Paderborn University}, author={Brede, Mathis}, year={2021} }


Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib

J.W. Rehnen, Bachelorarbeit, 2021

@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner}, year={2021} }


Evaluation of a ReconOS-ROS Combination based on a Video Processing Application

L. Henke, Bachelorarbeit, 2020

Robots are becoming increasingly autonomous and more capable. Because of a limited portable energy budget by e.g. batteries, and more demanding algorithms, an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs) for example can provide fast and efficient processing and the Robot Operating System (ROS) is a popular middleware used for robotic applications. The novel ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework for integrating reconfigurable hardware. It provides a unified interface between software and hardware. ReconROS is evaluated in this thesis by implementing a Sobel filter as the video processing application, running on a Zynq-7000 series System on Chip. Timing measurements were taken of execution and transfer times and were compared to theoretical values. Designing the hardware implementation is done by C code using High Level Synthesis and with the interface and functionality provided by ReconROS. An important aspect is the publish/subscribe mechanism of ROS. The Operating System interface functions for publishing and subscribing are reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces consistency to the execution times and performs twice as fast as the software implementation.

@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020} }


Implementing Machine Learning Functions as PYNQ FPGA Overlays

S. Thiele, Bachelorarbeit, 2020

@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ FPGA Overlays}, author={Thiele, Simon}, year={2020} }


Static Scheduling Algorithms for Heterogeneous Compute Nodes

J. Schnuer, Bachelorarbeit, Universität Paderborn, 2018

@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }


Evaluation of OpenCL-based Compilation for FPGAs

M. Croce, Bachelorarbeit, Universität Paderborn, 2018

@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }


Enforcing IP Core Connection Properties with Verifiable Security Monitors

F.P. Jentzsch, Bachelorarbeit, Universität Paderborn, 2018

@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }


An FPGA Accelerator for Checking Resolution Proofs

T. Hansmeier, Bachelorarbeit, Universität Paderborn, 2017

@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }


An AR-based Training and Assessment System for Myoelectrical Prosthetic Control

C. Kaltschmidt, Bachelorarbeit, Paderborn University, 2017

@book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }


Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung

M. Schmidt, Bachelorarbeit, Paderborn University, 2016

@book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }


Custom Memory Controller for ReconOS

S. Hermansen, Bachelorarbeit, Paderborn University, 2016

@book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }


Beschleunigte Simulation elektrischer Stromnetze mit GPUs

J. Horstmann, Bachelorarbeit, Paderborn University, 2016

@book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }


Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten

C. Knorr, Bachelorarbeit, Universität Paderborn, 2015

@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }


Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs

R. Meißner, Bachelorarbeit, Universität Paderborn, 2015

@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }


The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores

C. Rüthing, Bachelorarbeit, Paderborn University, 2014

@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }


Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten

C. Hagedorn, Bachelorarbeit, Paderborn University, 2014

@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn University}, author={Hagedorn, Christoph}, year={2014} }


EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese

F. König, Bachelorarbeit, Paderborn University, 2014

@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }


Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board

A. Bockhorn, Bachelorarbeit, Paderborn University, 2014

@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn, Arne}, year={2014} }


Behavior Models for Electric Vehicles

M. Knoop, Bachelorarbeit, IWES Kassel, 2013

@book{Knoop_2013, title={Behavior Models for Electric Vehicles}, publisher={IWES Kassel}, author={Knoop, Michael}, year={2013} }


Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors

B. Nofen, Bachelorarbeit, Paderborn University, 2013

@book{Nofen_2013, title={Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors}, publisher={Paderborn University}, author={Nofen, Barbara}, year={2013} }


Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs

D. Pudelko, Bachelorarbeit, Paderborn University, 2013

@book{Pudelko_2013, title={Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs}, publisher={Paderborn University}, author={Pudelko, Daniel}, year={2013} }


MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung

A. Sprenger, Bachelorarbeit, Paderborn University, 2013

@book{Sprenger_2013, title={MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung}, publisher={Paderborn University}, author={Sprenger, Alexander}, year={2013} }


Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen

P. Steppeler, Bachelorarbeit, Paderborn University, 2013

@book{Steppeler_2013, title={Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen}, publisher={Paderborn University}, author={Steppeler, Philipp}, year={2013} }


Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner

C. Bick, Bachelorarbeit, Paderborn University, 2013

@book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick, Christian}, year={2013} }


Stereo Matching on a HC-1 Hybrid Core Computer

H. Schmitz, Bachelorarbeit, Paderborn University, 2012

@book{Schmitz_2012, title={Stereo Matching on a HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Schmitz, Henning}, year={2012} }


Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System

C. Topmöller, Bachelorarbeit, Paderborn University, 2012

@book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }


Generating Adjustable Temperature Gradients on modern FPGAs

H. Hangmann, Bachelorarbeit, Paderborn University, 2012

@book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }


PinSim: Schnelle Simulation mit Pintools

N. Ikonomakis, Bachelorarbeit, Paderborn University, 2011

@book{Ikonomakis_2011, title={PinSim: Schnelle Simulation mit Pintools}, publisher={Paderborn University}, author={Ikonomakis, Nikolaos}, year={2011} }


MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern

H. Kassner, Bachelorarbeit, Paderborn University, 2011

@book{Kassner_2011, title={MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern}, publisher={Paderborn University}, author={Kassner, Hendrik}, year={2011} }


Soft Microprocessors with tightly coupled Application-Specific Coprocessors

D. Dridger, Bachelorarbeit, Paderborn University, 2010

@book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010} }


Parallelization of the UCT Algorithm on HPC-Clusters

T. Graf, Bachelorarbeit, Paderborn University, 2010

@book{Graf_2010, title={Parallelization of the UCT Algorithm on HPC-Clusters}, publisher={Paderborn University}, author={Graf, Tobias}, year={2010} }


Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS

B. Wildenhain, Bachelorarbeit, Paderborn University, 2009

@book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain, Benedikt}, year={2009} }


Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme

J. Niklas, Bachelorarbeit, Paderborn University, 2008

@book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }


Raytracing on a Custom Instruction Set CPU

M. Östermann, Bachelorarbeit, Paderborn University, 2008

@book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }


Design and Evaluation of MicroBlaze Multi-core Architectures

N. Westerheide, Bachelorarbeit, Paderborn University, 2008

@book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }


Selbstoptimierender Cache-Kontroller

D. Breitlauch, Bachelorarbeit, Paderborn University, 2008

@book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }


Verteilte Simulation von mobilen Robotern mit EyeSim

T. Ceylan, C. Yalcin, Bachelorarbeit, Paderborn University, 2008

@book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }


Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf

T. Knieper, Bachelorarbeit, Paderborn University, 2008

@book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }


Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen

A. Boschmann, Bachelorarbeit, Paderborn University, 2008

@book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }


VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen

R. Meiche, Bachelorarbeit, Paderborn University, 2007

@book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }


Distributed Simulation of mobile Robots using EyeSim

T. Ceylan, C. Yalcin, Bachelorarbeit, Paderborn University, 2007

@book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }


FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks

R. Mühlenbernd, Bachelorarbeit, Paderborn University, 2006

@book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }


Liste im Research Information System öffnen

Master's Theses


Liste im Research Information System öffnen

Design and Implementation of a ReconROS-based Obstacle Avoidance System

M.A. Sheikh, Masterarbeit, Paderborn University, 2021

Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which can contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption.

@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh, Muhammad Aamir}, year={2021} }


A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes

C. Kashikar, Masterarbeit, Paderborn University, 2021

Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique.

@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay}, year={2021} }


Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture

F.P. Jentzsch, Masterarbeit, 2020

Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware. This thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable computing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.

@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020} }


Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis

K. Chandrakar, Masterarbeit, 2020

@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020} }


Extension and Evaluation of Python-based High-Level Synthesis Tool Flows

V. Jaganath, Masterarbeit, 2020

@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }


A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking

M. Keerthipati, Masterarbeit, Universität Paderborn, 2019

Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.

@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati, Monica}, year={2019} }


Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip

J. Mehta, Masterarbeit, 2019

@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip}, author={Mehta, Jinay}, year={2019} }


Implementing a Real-time System on a Platform FPGA operated with ReconOS

C. Lienen, Masterarbeit, Universität Paderborn, 2019

@book{Lienen, title={Implementing a Real-time System on a Platform FPGA operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian} }


Incremental learning with Support Vector Machine on embedded platforms

S. Kumar Jeyakumar, Masterarbeit, 2019

@book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019} }


FPGA Acceleration of String Search Techniques in Huge Data Sets

N.S. Sabu, Masterarbeit, Paderborn University, 2019

@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019} }


Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers

T. Hansmeier, Masterarbeit, Universität Paderborn, 2019

@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }


Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data

L. Clausing, Masterarbeit, Ruhr-University Bochum, 2018

@book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }


OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten

C. Knorr, Masterarbeit, Universität Paderborn, 2017

@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }


A Framework for the Synthesis of Approximate Circuits

L.M. Witschen, Masterarbeit, Universität Paderborn, 2017

@book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }


Reconfigurable Cryptographic Services

A. Dietrich, Masterarbeit, Paderborn University, 2017

@book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn University}, author={Dietrich, Andreas}, year={2017} }


Acceleration of Industrial Analytics Functions on a Platform FPGA

U. Riaz, Masterarbeit, Paderborn University, 2017

@book{Riaz_2017, title={Acceleration of Industrial Analytics Functions on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017} }


Operating System Support for Reconfigurable Cache

V. Makeswaran, Masterarbeit, Paderborn University, 2016

@book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }


Private/Shared Data Classification and Implementation for a Multi-Softcore Platform

I. Ibne Ashraf, Masterarbeit, Paderborn University, 2016

@book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }


Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion

J. Cedric Mertens, Masterarbeit, Paderborn University, 2016

@book{Cedric Mertens_2016, title={Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion}, publisher={Paderborn University}, author={Cedric Mertens, Jan}, year={2016} }


Implementation of Bilinear Pairings on Reconfigurable Hardware

A.S. Nassery, Masterarbeit, Paderborn University, 2016

@book{Nassery_2016, title={Implementation of Bilinear Pairings on Reconfigurable Hardware}, publisher={Paderborn University}, author={Nassery, Abdul Sami}, year={2016} }


Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method

O. Amin, Masterarbeit, Paderborn University, 2016

@book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }


Acceleration of Artificial Neural Networks on a Zynq Platform

T. Posewsky, Masterarbeit, Paderborn University, 2015

@book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }


Evolution of Heat Flow Prediction Models for FPGA Devices

H. Hangmann, Masterarbeit, Paderborn University, 2015

@book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }


Computer Vision basierte Klassifikation von HD EMG Signalen

C. Haupt, Masterarbeit, Paderborn University, 2015

@book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }


Self-Optimizing Organic Cache

A.F. Ahmed, Masterarbeit, Paderborn University, 2015

@book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }


Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA

B. Koch, Masterarbeit, Paderborn University, 2014

@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin}, year={2014} }


Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs

R. Mittendorf, Masterarbeit, Paderborn University, 2014

@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }


Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA

S. Surmund, Masterarbeit, Paderborn University, 2014

@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }


A Generalized Loop Accelerator Implemented as a Coarse-Grained Array

M. Brand, Masterarbeit, Paderborn University, 2014

@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel}, year={2014} }


Easy-to-use-on-the-fly binary program acceleration on many-cores

M. Damschen, Masterarbeit, Paderborn University, 2014

@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014} }


Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs

H. Riebler, Masterarbeit, Paderborn University, 2013

@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Paderborn University}, author={Riebler, Heinrich}, year={2013} }


Analysis of Pattern Based Model Design and Learning in Computer-Go

M. Wistuba, Masterarbeit, Paderborn University, 2012

@book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }


Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer

D. Dridger, Masterarbeit, Paderborn University, 2012

@book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }


Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go

T. Graf, Masterarbeit, Paderborn University, 2012

@book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }


Analysis of Algorithmic Approaches for Temporal Partitioning

A. Schwabe, Masterarbeit, Paderborn University, 2011

@book{Schwabe_2011, title={Analysis of Algorithmic Approaches for Temporal Partitioning}, publisher={Paderborn University}, author={Schwabe, Arne}, year={2011} }


User Space Scheduling for Heterogeneous Systems

D. Welp, Masterarbeit, Paderborn University, 2011

@book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems}, publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }


FPGA/CPU Multicore-Plattform für ReconOS/eCos

R. Meiche, Masterarbeit, Paderborn University, 2010

@book{Meiche_2010, title={FPGA/CPU Multicore-Plattform für ReconOS/eCos}, publisher={Paderborn University}, author={Meiche, Robert}, year={2010} }


Transparente Hardwarebeschleunigung durch Shared Library Interposing

M. Niekamp, Masterarbeit, Paderborn University, 2010

@book{Niekamp_2010, title={Transparente Hardwarebeschleunigung durch Shared Library Interposing}, publisher={Paderborn University}, author={Niekamp, Manuel}, year={2010} }


A Token-Ring Network-On-Chip for Message Passing in ReconOS

B. Runde, Masterarbeit, Paderborn University, 2010

@book{Runde_2010, title={A Token-Ring Network-On-Chip for Message Passing in ReconOS}, publisher={Paderborn University}, author={Runde, Bodo}, year={2010} }


Scheduling Support for Heterogeneous Hardware Accelerators under Linux

T. Wiersema, Masterarbeit, Paderborn University, 2010

@book{Wiersema_2010, title={Scheduling Support for Heterogeneous Hardware Accelerators under Linux}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2010} }


Evolvable Cache Controller

D. Breitlauch, Masterarbeit, Paderborn University, 2010

@book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2010} }


Hybridization of Global Multi-Objective and Local Search Techniques

T. Knieper, Masterarbeit, Paderborn University, 2010

@book{Knieper_2010, title={Hybridization of Global Multi-Objective and Local Search Techniques}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2010} }


EMG-basierte Ganganalyse

A. Boschmann, Masterarbeit, Paderborn University, 2010

@book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2010} }


Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen

A. Agne, Masterarbeit, Paderborn University, 2010

@book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne, Andreas}, year={2010} }


Evolvable Robot Controller

A. Kostin, Masterarbeit, Paderborn University, 2009

@book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn University}, author={Kostin, Alexander}, year={2009} }


Compiler for a Custom Instruction Set CPU

M. Tofall, Masterarbeit, Paderborn University, 2009

@book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Tofall, Martin}, year={2009} }


Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units

A. Warkentin, Masterarbeit, Paderborn University, 2009

@book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin, Alexander}, year={2009} }


Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern

M. Happe, Masterarbeit, Paderborn University, 2008

@book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }


Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS

W. Reisch, Masterarbeit, Paderborn University, 2007

@book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }


Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem

E. Rethmeier, Masterarbeit, Paderborn University, 2007

@book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }


A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization

B. Defo, Masterarbeit, Paderborn University, 2007

@book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }


Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme

S. Döhre, Masterarbeit, Paderborn University, 2007

@book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }


Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen

T. Beisel, Masterarbeit, Paderborn University, 2007

@book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }


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Dissertations


Liste im Research Information System öffnen

Frameworks and Methodologies for Search-based Approximate Logic Synthesis

L.M. Witschen, 2022

@book{Witschen_2022, title={Frameworks and Methodologies for Search-based Approximate Logic Synthesis}, DOI={10.17619/UNIPB/1-1649}, author={Witschen, Linus Matthias}, year={2022} }


Hardware Trojans in Reconfigurable Computing

Q.A. Ahmed, Paderborn University, Paderborn, Germany, 2022

The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques.

@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={10.17619/UNIPB/1-1271}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }


Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware

T. Wiersema, Paderborn University, 2021

Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen, Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem größeren Kontext signifikant. Diese Dissertation schließt die Lücke zwischen PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale. Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt werden können.

@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2021} }


FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization

N. Ho, Universität Paderborn, 2018

Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion. Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen, kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware. Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen, wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz im Vergleich zu konventionellen Caches erhöhen können.

@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }


Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing

T. Beisel, Logos Verlag Berlin GmbH, 2015

The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.

@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }


Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go

L. Schäfers, Logos Verlag Berlin GmbH, 2014

Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.

@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }


Performance and thermal management on self-adaptive hybrid multi-cores

M. Happe, Logos Verlag Berlin GmbH, 2013

Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time.

@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }


Adapting Hardware Systems by Means of Multi-Objective Evolution

P. Kaufmann, Logos Verlag Berlin GmbH, 2013

Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.

@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }


Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security

S. Drzevitzky, Universität Paderborn, 2012

FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit.

@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }


Design and Programming of Reconfigurable Mesh based Many-Cores

H. Giefers, Logos Verlag Berlin GmbH, 2012

The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.

@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }


Liste im Research Information System öffnen

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