• 2018-07-15 Clarified deadline for submission of reviews (16 July, 23:59 hours)
• 2018-07-03 Added slides for reviewing and presenting scientific papers
• 2018-05-15 Corrected typo in schedule. The seminar is planned for 23 + 24 July (not 22 + 23 July as erroneously stated)
• 2018-05-14 Added list of conferences and journals in the area of the seminar
• 2018-05-14 Uploaded slides from initial meeting, updated schedule, uploaded LaTeX template for seminar paper.
• 2018-05-09 Updated schedule and fixed a couple of minor spelling mistakes.
• 2018-04-25 The appointment for the first lecture had to be cancelled. I will schedule a replacement appointment.

Accelerators with Field-Programmable Gate Arrays (FPGAs) are an emerging and promising technology to accelerate and improve the energy efficiency of many important data center and high-performance computing workloads. Over the last two decades, numerous works have investigated suitable FPGA hardware and system architectures, application domains, and development toolflows and demonstrated the potential of the technology. Very recently, hyperscale cloud data center providers (Microsoft, Amazon, Baidu, and others) have deployed FPGAs also in their production systems for accelerating their own applications or as an infastructure (IaaS) for customers. The Paderborn Center for Parallel Computing (PC²) is also playing a pioneering role in this development by deploying FPGAs in their next generation HPC system.

The topic of this seminar will be to study FPGAs for high-performance data center workloads and high-performance computing. The topics will cover the complete stack from architecture to development tools to applications.

This seminar is also in ideal preparation for a CS/CE project group in the area of "High-Performance Computing with FPGAs", which will start in Winter term 2018/19 and will also be taught by our group.

The seminar builds on knowledge from Bachelor and Master-level courses in the area of computer engineering, such as Computer Architecture, Digital Design, Reconfigurable Computing, or High-Performance Computing. Having attended these courses is not a strict precondition. But you should have at least a good general understanding in one of these areas.

The seminar will be taught in English.
 

Admission

Attendance will be limited to 20 persons based on the first come, first served policy implemented by PAUL.

Assignment of Topics

A list of topics will be published on this website by April 20. The assignment of topics will happen during the first seminar meeting, which will take place on April, 27 at 16:00 in room O2.267.

Schedule

Please find a list for lectures, meetings and submission deadlines below:

1. Seminar lecture + topics assignment: 9 May, 16:15-18:00 in room O4.267
2. Lecture: reading and writing scientific papers: 9 May, 16:15-18:00 in room O4.267
3. Meeting with supervisor: discussion of paper outline and bibliography, 4 or 5 June, timeslot scheduled individually
4. Submission of draft paper: 2 July 16:00
5. Lecture: reviewing papers and presenting scientific talks: 2 July 16:15-18:00 (room TBD)
6. Meeting with supervisor: discussion of draft presentation: 12 or 13 July, timeslot scheduled individually
7. Submission of reviews: 16 July 23:59
8. Seminar presentations: 23 and 24 July, 9:00-18:00 (tentative timing, will be updated later), (room TBD)
9. Submission of final paper: 17 August, midnight

All submission have to be performed by email to christian.plessl@uni-paderborn.de 

Lecture Slides

• Introduction to the seminar
• Reading scientific papers
• Writing scientific papers
• How to review scientific papers
• How to give a good research talk 

Templates

• LaTeX template for paper

List of conferences and journals in the area of the seminar

Conferences FPGA

• Int. Conf. on Field Programmable Logic and Applications (FPL)
• Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
• Int. Symp. on Field-Programmable Gate Arrays (FPGA)
• Int. Conf. on Field Programmable Technology (FPT)
• Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)

Conferences HPC

• Int. Conference on Supercomputing (SC)
• ISC High Performance (ISC)
• Int. Conf. on Supercomputing (ICS)
• Int. Symp. on Parallel and Distributed Processing (IPDPS)

Journals FPGA

• ACM Transactions on Reconfigurable Technology and Systems (TRETS)
• Hindawi International Journal of Reconfigurable Computing (IJRC)
• Elsevier Microprocessors and Microsystems

Journals HPC

• Wiley Concurrency and Computation: Practice and Experience (CCPE)
• ACM Transactions on Parallel Computing
• Journal of Supercomputing

By participating in the seminar, you agree to follow these rules. Not respecting these rules will result in failing the seminar:

• The attendance of the seminar lectures, all individual seminar meetings with the supervisor and the actual block seminar event is compulsory (requirement for attending first lecture has been waived due to postponing the first lecture)
• Each participant agrees to create a written review report for two other seminar papers (peer review).
• All deadlines for submitting documents are strict and not negotiable.
• The seminar papers have to be written with LaTeX using the provided template.
• Plagiarism is not acceptable and will result in failing the seminar.

The grade for the seminar will be assigned based on the following factors: quality of the paper, quality of the presentation, quality of the feedback given to fellow participants through peer review, active participation in the discussion during the block seminar.

A Survey and empirical studies of FPGA technology and tools

A1. System Architectures for FPGAs in Cloud Computing 

• Which providers are using or offering FPGAs resources in the cloud (Amazon, Microsoft, ..)
• What is the architecture of these systems (system integration, network, security considerations)?
• How can applications be deployed (supported tool-flows, business models)
• What applications use these infrastructures?

 A2. Customization of interconnects for parallel and distributed applications

• How are FPGAs used to build custom communication topologies and routers?
• What use-cases profit from these customized communication networks?
• How is the advanced functionality presented to the developer?

  A3. Technological Trends for FPGAs

• How have FPGAs developed over the last two decades regarding capacity and capability?
• What trends can be seen?

A4. Survey and empirical study of the use of FPGAs in HPC

• What applications have been targeted?
• What development flows have been used?
• What results have been achieved and what approach is used to compare them to the state of the art?

A5. High-Level Synthesis

• What are the general problems in high-level synthesis?
• What approaches exist that are specific to FPGAs?
• Which issues are well understood, what is currently being investigated, what questions are still open?

A6. Domain-specific compilation tools for FPGAs

• What domain-specific development tools have been proposed for FPGAs?
• On which technologies do these tools build?
• What results have been achieved?
• Which approaches have had a practical impact?

B Survey and analysis of the use of FPGAs for tacking problems in HPC

The following list presents a choice of established and emerging application domains where FPGAs have been successfully applied. Each seminar report shall discuss the following topics:

• Introduction and survey of the overall application domain
• Discussion of the specific advantages of FPGAs for the area over competing technologies
• Focus on a few specific and particularly relevant applications

The list of application domains is not final. If you have a specific interest, you may also propose additional fields. 

  B1. Deep neural networks
  B2. Binarized neural networks
  B3. Bioinformatics
  B4. Image Processing
  B5. Video Encoding
  B6. Financial Applications
  B7. Fast Fourier Transformation (FFT)
  B8. Molecular Dynamics
  B9. Database Acceleration
  B10. Regular Expressions
  B11. Stencil Computations
  B12. Software-Defined Networking
  B13. Tree algorithms
  B14. Linear Algebra with Sparse Matrices