Goals and Contents

SUS is a new Hardware Description Language (HDL) developed at PC2. Its goal is to allow for precise specification of any synchronous hardware circuit on FPGAs or ASIC technology, while avoiding some of the most time-consuming and error-prone efforts associated with traditional hardware design with HDLs. The unique feature of SUS is a latency counting system that enables easy and correct pipelining of individual and composed hardware modules.

The goal of this project is to use SUS to design one or more sparse linear algebra kernels like Sparse Matrix Vector multiplication (SpMV). A previous SpMV design to exploit the bandwidth capabilities of High-Bandwidth Memory (HBM) on Alveo U280 cards at PC2 has been developed with the High-Level Synthesis tool Vitis HLS, but involved several workarounds or compromises to approach the desired functionality. This project group will explore how SUS can be used to create such designs easier or with even higher quality of results.

In this project, you will

• In a tutorial phase get familiar with hardware design using SUS
• Learn how to deploy designs generated with SUS on the FPGAs operated at PC2
• Apply these techniques to one or more sparse linear algebra kernels

Resources

• https://sus-lang.org/
• https://github.com/pc2/sus-compiler
• https://doi.org/10.1109/fccm60383.2024.00014
• https://github.com/pc2/HiHiSpMV