Open and Running Thesis Projects

BT: Bachelor's Thesis
MT: Master's Thesis
BT/MT: Adjustable research question that can be formulated as either type

Open Thesis Projects

Topic	Project Type	Supervisor
Bring your own idea!	BT/MT	Marco Platzner
Implementation and Evaluation of Deep Differentiable Logic Gate Networks on FPGA	MT	Atousa Jafari
Hardware Trojans in Custom-tailored Dataflow Accelerators	MT	Qazi Arbab Ahmed
Hybrid approximation of DNNs using LogicNets	MT	Muhammad Awais
Survey of ROS FPGA Frameworks	MT	Alexander Nowosad
Implementation of a Performant and Easy-to-use Memory Interface for Recon(R)OS	MT	Alexander Nowosad

Project types:

Unless noted otherwise in the announcement, you can decide for yourself if you want to write your thesis in English or in German.

Topic	Project Type	Supervisor
A Simulator for Schedulability Experiments with Periodic Real-time Tasks on FPGAs	BA	Marco Platzner