Open and Running Thesis Projects
Open Thesis Projects
| Topic | Project Type | Supervisor |
|---|---|---|
| Bring your own idea! | BT/MT | Marco Platzner |
| Exploration and Acceleration of DNNs for Radio Signal Processing | MT | Felix Jentzsch |
| Efficient DNN Implementation on FPGA: Bring your own use case! | BT/MT | Felix Jentzsch |
Project types:
- BT: Bachelor's Thesis
- MT: Master's Thesis
- BT/MT: Adjustable research question that can be formulated as either type
Unless noted otherwise in the announcement, you can decide for yourself if you want to write your thesis in English or in German.
Running Thesis Projects
| Topic | Project Type | Supervisor |
|---|---|---|
| A Comparison of Algorithms for the Generation of Layouts based on Reconfigurable Slots on FPGAs | MT | Marco Platzner |
| Development of ReconOS/Zephyr on a RISC-V soft CPU | MT | Christian Lienen |
| RadioML Demonstrator on an RFSoC Platform | MT | Felix Jentzsch |
| Reconfigurable Random Forest Implementation on FPGA | MT | Lennart Clausing |
| Implementation and Evaluation of a ReconROS based Obstacle Avoidance Architecture | MT | Christian Lienen |
| Power Analysis of Embedded FPGA Accelerators | BT | Felix Jentzsch |