Con­fer­ence Pa­pers

The following list is still incomplete and will be updated shortly.

DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: To Apear in IEEE ISVLSI 2024, 2024.

Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML

F. Jentzsch, in: 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2023.

AutonomROS: A ReconROS-based Autonomous Driving Unit

C. Lienen, M. Brede, D. Karger, K. Koch, D. Logan, J. Mazur, A.P. Nowosad, A. Schnelle, M. Waizy, M. Platzner, in: 2023 Seventh IEEE International Conference on Robotic Computing (IRC), IEEE, 2023.

Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms

C. Lienen, A.P. Nowosad, M. Platzner, in: Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI), n.d.

fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications

C. Lienen, S.H. Middeke, M. Platzner, in: Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), 2023.

On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64

L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, M. Platzner, in: Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023.

MAAS: Hiding Trojans in Approximate Circuits

Q.A. Ahmed, M. Awais, M. Platzner, in: The 24th International Symposium on Quality Electronic Design (ISQED’23), San Francisco, Califorina USA, 2023.

On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs

Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), Pafos, Cyprus, 2022.

Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications

C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System Design (DSD), n.d.

XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion

T. Hansmeier, M. Brede, M. Platzner, in: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2022, pp. 2071–2079.

ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support

L. Clausing, M. Platzner, in: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–127.

Integrating Safety Guarantees into the Learning Classifier System XCS

T. Hansmeier, M. Platzner, in: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Springer International Publishing, 2022, pp. 386–401.

MUSCAT: MUS-based Circuit Approximation Technique

L.M. Witschen, T. Wiersema, M. Artmann, M. Platzner, in: Design, Automation and Test in Europe (DATE), n.d.

Search Space Characterization for Approximate Logic Synthesis

L.M. Witschen, T. Wiersema, L.D. Reuter, M. Platzner, in: 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d.

FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics

H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.

ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip

L. Clausing, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2021.

Malicious Routing: Circumventing Bitstream-level Verification for FPGAs

Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.

Hardware Trojans in Reconfigurable Computing

Q.A. Ahmed, in: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC), 2021.

Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS

T. Hansmeier, in: HEART ’21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Association for Computing Machinery (ACM), New York, NY, United States, 2021.

An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS

T. Hansmeier, M. Platzner, in: GECCO ’21: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2021, pp. 1639–1647.

Timing Optimization for Virtual FPGA Configurations

L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner, in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes in Computer Science, n.d.

Design of Distributed Reconfigurable Robotics Systems with ReconROS

C. Lienen, M. Platzner, ArXiv:2107.07208 (2021).

MCTS-Based Synthesis Towards Efficient Approximate Accelerators

M. Awais, M. Platzner, in: Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, 2021, pp. 384–389.

LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.

MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes

A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 6–16.

MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes

A. Lösch, M. Platzner, in: 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020.

Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices

Z. Guetttatfi, P. Kaufmann, M. Platzner, in: Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC), 2020.

Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures

C.P. Gatica, M. Platzner, in: Machine Learning for Cyber Physical Systems (ML4CPS 2017), Berlin, Heidelberg, 2020.

Search Space Characterization for AxC Synthesis

L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.).

ReconROS: Flexible Hardware Acceleration for ROS2 Applications

C. Lienen, M. Platzner, B. Rinner, in: Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT), 2020.

An Adaption Mechanism for the Error Threshold of XCSF

T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 1756–1764.

Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold

T. Hansmeier, P. Kaufmann, M. Platzner, in: GECCO ’20: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2020, pp. 125–126.

A Hybrid Synthesis Methodology for Approximate Circuits

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.

Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan

Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch, R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International Publishing, Cham, 2019, pp. 127–136.

An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware

Z. Guettatfi, M. Platzner, O. Kermia, A. Khouas, in: 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2019.

Jump Search: A Fast Technique for the Synthesis of Approximate Circuits

L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth Workshop on Approximate Computing (AxC 2019) (n.d.).

Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor

N. Ho, P. Kaufmann, M. Platzner, in: World Congress on Nature and Biologically Inspired Computing (NaBIC), Springer, 2019.

Jump Search: A Fast Technique for the Synthesis of Approximate Circuits

L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings of the 2019 on Great Lakes Symposium on VLSI  - GLSVLSI ’19, ACM, New York, NY, USA, 2019.

A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes

A. Lösch, M. Platzner, in: 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), IEEE, 2018.

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation

L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Third Workshop on Approximate Computing (AxC 2018) (n.d.).

Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes

A. Lösch, A. Wiens, M. Platzner, in: Proceedings of the International Conference on Architecture of Computing Systems (ARCS), Springer International Publishing, Cham, 2018, pp. 73–84.

An FPGA/HMC-Based Accelerator for Resolution Proof Checking

T. Hansmeier, M. Platzner, D. Andrews, in: ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications, Springer International Publishing, 2018, pp. 153–165.

Making the Case for Proof-carrying Approximate Circuits

L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018).

An MCTS-based Framework for Synthesis of Approximate Circuits

M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.

reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements

A. Lösch, M. Platzner, in: Proceedings of the 28th Annual IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2017.

I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems

I. Ghribi, R.B. Abdallah, M. Khalgui, M. Platzner, in: Communications in Computer and Information Science, Springer , Cham, 2017.

Parametrizing Cartesian Genetic Programming: An Empirical Study

P. Kaufmann, R. Kalkreuth, in: KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI, Springer International Publishing, 2017.

Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches

P. Kaufmann, N. Ho, M. Platzner, in: Adaptive Hardware and Systems (AHS), IEEE, 2017.

An Empirical Study on the Parametrization of Cartesian Genetic Programming

P. Kaufmann, R. Kalkreuth, in: Genetic and Evolutionary Computation (GECCO), Compendium, ACM, 2017.

Computational self-awareness as design approach for visual sensor nodes

Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.

A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller

A. Boschmann, G. Thombansen, L.M. Witschen, A. Wiens, M. Platzner, in: Design, Automation and Test in Europe (DATE), 2017.

Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor

N. Ho, I.I. Ashraf, P. Kaufmann, M. Platzner, in: Proc. Design, Automation and Test in Europe Conf. (DATE), 2017.

Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor

N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center

A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.

FPGA-based acceleration of high density myoelectric signal processing

A. Boschmann, A. Agne, L. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.

FPGA-based acceleration of high density myoelectric signal processing

A. Boschmann, A. Agne, L.M. Witschen, G. Thombansen, F. Kraus, M. Platzner, in: 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2016.

Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware

T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.

Using Deep Convolutional Neural Networks in Monte Carlo Tree Search

T. Graf, M. Platzner, in: Computer and Games, 2016.

Monte-Carlo Simulation Balancing Revisited

T. Graf, M. Platzner, in: IEEE Computational Intelligence and Games, 2016.

Thread Shadowing: On the Effectiveness of Error Detection at the Hardware Thread Level

S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2016 International Conference On, 2016, pp. 1–8.

RCo-Design: New Visual Environment for Reconfigurable Embedded Systems

I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 30th European Simulation and Modelling Conference (ESM), 2016.

New Co-design Methodology for Real-time Embedded Systems

I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 11th International Conference on Software Engineering and Applications (ICSOFT-EA), 2016, pp. 185–195.

A novel immersive augmented reality system for prosthesis training and assessment

A. Boschmann, S. Dosen, A. Werner, A. Raies, D. Farina, in: Proc. IEEE Int. Conf. Biomed. Health Informatics (BHI), 2016.

Boolean Difference Based Reliability Evaluation of Fault Tolerant Circuit Structures on FPGAs

J. Anwer, M. Platzner, in: Euromicro Conference on Digital System Design (DSD), 2016.

Transparent offloading of computational hotspots from binary code to Xeon Phi

M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm

J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores

M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.

On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach

T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.

Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning

T. Graf, M. Platzner, in: Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers, Springer International Publishing, 2015, pp. 1–11.

Comparison of thread signatures for error detection in hybrid multi-cores

S. Meisner, M. Platzner, in: Field Programmable Technology (FPT), 2015 International Conference On, 2015, pp. 212–215.

Significant papers from the first 25 years of the FPL conference

P. H.W. Leong, H. Amano, J. Anderson, K. Bertels, J. M.P. Cardoso, O. Diessel, G. Gogniat, M. Hutton, J. Lee, W. Luk, P. Lysaght, M. Platzner, V. K. Prasanna, T. Rissa, C. Silvano, H. So, Y. Wang, in: Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, pp. 1–3.

New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software

I. Ghribi, R. Ben Abdallah, M. Khalgui, M. Platzner, in: Proceedings of the 29th European Simulation and Modelling Conference (ESM), 2015.

On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI, IEEE, 2015, pp. 491–496.

Fault modeling in controllable polarity silicon nanowire circuits

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453–458.

Over effective hard real-time hardware tasks scheduling and allocation

Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.

Microarchitectural optimization by means of reconfigurable and evolvable cache mappings

N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.

Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing

P. Kaufmann, C. Shen, in: Genetic and Evolutionary Computation (GECCO), ACM, 2015, pp. 409–416.

Deferring Accelerator Offloading Decisions to Application Runtime

G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

Kernel-Centric Acceleration of High Accuracy Stereo-Matching

T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.

SAVE: Towards efficient resource management in heterogeneous system architectures

G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach

G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer

T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.

Reconstructing AES Key Schedules from Decayed Memory with FPGAs

H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.

Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA

T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.

Integrating Software and Hardware Verification

M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.

Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring

T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.

Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection

S. Meisner, M. Platzner, in: D. Goehringer, M. Santambrogio, J.P. Cardoso, K. Bertels (Eds.), Proceedings of the 10th International Symposium on Applied Reconfigurable Computing (ARC), Springer, 2014, pp. 283–290.

On Semeai Detection in Monte-Carlo Go

T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.

Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go

T. Graf, M. Platzner, in: 2014 IEEE Conference on Computational Intelligence and Games, 2014, pp. 1–8.

Optimizing the Generator Start-up Sequence After a Power System Blackout

C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014.

A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm

C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014.

Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs

J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection

H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–168.

A computer vision-based approach to high density EMG pattern recognition using structural similarity

A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC), 2014.

Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity

A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.

Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System

K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC), 2014.

A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms

N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.

Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure

N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.

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