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Teaching Show image information

Teaching

Running Thesis Projects

  • Evaluation and Development of a Python-to-Hardware Tool Flow. Master's Thesis. Supervised by Lennart Clausing.
  • Implementing Machine Learning (ML) Python Library Functions on an FPGA. Bachelor's Thesis. Supervised by Lennart Clausing.
  • Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. Master's Thesis. Supervised by Christian Lienen.
  • Evaluation of a ReconOS-ROS Combination based on a Video Processing Application. Bachelor's Thesis. Supervised by Christian Lienen.

Completed Thesis Projects

Bachelor's Theses


Open list in Research Information System

Evaluation of OpenCL-based Compilation for FPGAs

M. Croce, Bachelor's thesis, Universität Paderborn, 2018

@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs}, publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }


    Static Scheduling Algorithms for Heterogeneous Compute Nodes

    J. Schnuer, Bachelor's thesis, Universität Paderborn, 2018

    @book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip}, year={2018} }


      Enforcing IP Core Connection Properties with Verifiable Security Monitors

      F.P. Jentzsch, Bachelor's thesis, Universität Paderborn, 2018

      @book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch, Felix Paul}, year={2018} }


        An FPGA Accelerator for Checking Resolution Proofs

        T. Hansmeier, Bachelor's thesis, Universität Paderborn, 2017

        @book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017} }


          An AR-based Training and Assessment System for Myoelectrical Prosthetic Control

          C. Kaltschmidt, Bachelor's thesis, Paderborn University, 2017

          @book{Kaltschmidt_2017, title={An AR-based Training and Assessment System for Myoelectrical Prosthetic Control}, publisher={Paderborn University}, author={Kaltschmidt, Christian}, year={2017} }


            Beschleunigte Simulation elektrischer Stromnetze mit GPUs

            J. Horstmann, Bachelor's thesis, Paderborn University, 2016

            @book{Horstmann_2016, title={Beschleunigte Simulation elektrischer Stromnetze mit GPUs}, publisher={Paderborn University}, author={Horstmann, Jens}, year={2016} }


              Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung

              M. Schmidt, Bachelor's thesis, Paderborn University, 2016

              @book{Schmidt_2016, title={Konzeption und Implementierung einer digitalen Ansteuerung für den Betrieb einer elektrischen Sendereinheit für induktive Energieübertragung}, publisher={Paderborn University}, author={Schmidt, Marco}, year={2016} }


                Custom Memory Controller for ReconOS

                S. Hermansen, Bachelor's thesis, Paderborn University, 2016

                @book{Hermansen_2016, title={Custom Memory Controller for ReconOS}, publisher={Paderborn University}, author={Hermansen, Sven}, year={2016} }


                  Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs

                  R. Meißner, Bachelor's thesis, Universität Paderborn, 2015

                  @book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner, Roland}, year={2015} }


                    Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten

                    C. Knorr, Bachelor's thesis, Universität Paderborn, 2015

                    @book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2015} }


                      Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board

                      A. Bockhorn, Bachelor's thesis, Paderborn University, 2014

                      @book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn, Arne}, year={2014} }


                        Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten

                        C. Hagedorn, Bachelor's thesis, Paderborn University, 2014

                        @book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn University}, author={Hagedorn, Christoph}, year={2014} }


                          EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese

                          F. König, Bachelor's thesis, Paderborn University, 2014

                          @book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }


                            The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores

                            C. Rüthing, Bachelor's thesis, Paderborn University, 2014

                            @book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }


                              Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner

                              C. Bick, Bachelor's thesis, Paderborn University, 2013

                              @book{Bick_2013, title={Beschleunigung von Tiefenberechnung aus Stereobildern durch FPGA-basierte Datenflussrechner}, publisher={Paderborn University}, author={Bick, Christian}, year={2013} }


                                Behavior Models for Electric Vehicles

                                M. Knoop, Bachelor's thesis, IWES Kassel, 2013

                                @book{Knoop_2013, title={Behavior Models for Electric Vehicles}, publisher={IWES Kassel}, author={Knoop, Michael}, year={2013} }


                                  Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors

                                  B. Nofen, Bachelor's thesis, Paderborn University, 2013

                                  @book{Nofen_2013, title={Verbesserung der Erkennungsrate eines Systems zur Klassifikation von EMG-Signalen durch den Einsatz eines hybriden Lagesensors}, publisher={Paderborn University}, author={Nofen, Barbara}, year={2013} }


                                    Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs

                                    D. Pudelko, Bachelor's thesis, Paderborn University, 2013

                                    @book{Pudelko_2013, title={Überquerung der Styx - Betriebsparametervariation und Fehlerverhalten eines Platform FPGAs}, publisher={Paderborn University}, author={Pudelko, Daniel}, year={2013} }


                                      MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung

                                      A. Sprenger, Bachelor's thesis, Paderborn University, 2013

                                      @book{Sprenger_2013, title={MiBenchHybrid : Erweiterung eines Benchmarks um Hardwarebeschleunigung}, publisher={Paderborn University}, author={Sprenger, Alexander}, year={2013} }


                                        Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen

                                        P. Steppeler, Bachelor's thesis, Paderborn University, 2013

                                        @book{Steppeler_2013, title={Beschleunigung von Einzelbild-Erkennungsverfahren auf Datenfluss basierenden HPC Systemen}, publisher={Paderborn University}, author={Steppeler, Philipp}, year={2013} }


                                          Generating Adjustable Temperature Gradients on modern FPGAs

                                          H. Hangmann, Bachelor's thesis, Paderborn University, 2012

                                          @book{Hangmann_2012, title={Generating Adjustable Temperature Gradients on modern FPGAs}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2012} }


                                            Stereo Matching on a HC-1 Hybrid Core Computer

                                            H. Schmitz, Bachelor's thesis, Paderborn University, 2012

                                            @book{Schmitz_2012, title={Stereo Matching on a HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Schmitz, Henning}, year={2012} }


                                              Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System

                                              C. Topmöller, Bachelor's thesis, Paderborn University, 2012

                                              @book{Topmöller_2012, title={Entwicklung eines Picoblaze Compilers mit dem Gentle Compiler Construction System}, publisher={Paderborn University}, author={Topmöller, Christoph}, year={2012} }


                                                PinSim: Schnelle Simulation mit Pintools

                                                N. Ikonomakis, Bachelor's thesis, Paderborn University, 2011

                                                @book{Ikonomakis_2011, title={PinSim: Schnelle Simulation mit Pintools}, publisher={Paderborn University}, author={Ikonomakis, Nikolaos}, year={2011} }


                                                  MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern

                                                  H. Kassner, Bachelor's thesis, Paderborn University, 2011

                                                  @book{Kassner_2011, title={MPI-CUDA Codegenerierung für Nanophoton Simulationen auf Clustern}, publisher={Paderborn University}, author={Kassner, Hendrik}, year={2011} }


                                                    Soft Microprocessors with tightly coupled Application-Specific Coprocessors

                                                    D. Dridger, Bachelor's thesis, Paderborn University, 2010

                                                    @book{Dridger_2010, title={Soft Microprocessors with tightly coupled Application-Specific Coprocessors}, publisher={Paderborn University}, author={Dridger, Denis}, year={2010} }


                                                      Parallelization of the UCT Algorithm on HPC-Clusters

                                                      T. Graf, Bachelor's thesis, Paderborn University, 2010

                                                      @book{Graf_2010, title={Parallelization of the UCT Algorithm on HPC-Clusters}, publisher={Paderborn University}, author={Graf, Tobias}, year={2010} }


                                                        Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS

                                                        B. Wildenhain, Bachelor's thesis, Paderborn University, 2009

                                                        @book{Wildenhain_2009, title={Implementierung von Kryptographie-Hardwarebeschleunigern für das HW/SW-Betriebssystem ReconOS}, publisher={Paderborn University}, author={Wildenhain, Benedikt}, year={2009} }


                                                          Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen

                                                          A. Boschmann, Bachelor's thesis, Paderborn University, 2008

                                                          @book{Boschmann_2008, title={Aufbau und experimentelle Bewertung eines Systems zur Langzeitklassifikation von EMG-Signalen}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2008} }


                                                            Verteilte Simulation von mobilen Robotern mit EyeSim

                                                            T. Ceylan, C. Yalcin, Bachelor's thesis, Paderborn University, 2008

                                                            @book{Ceylan_Yalcin_2008, title={Verteilte Simulation von mobilen Robotern mit EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2008} }


                                                              Selbstoptimierender Cache-Kontroller

                                                              D. Breitlauch, Bachelor's thesis, Paderborn University, 2008

                                                              @book{Breitlauch_2008, title={Selbstoptimierender Cache-Kontroller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2008} }


                                                                Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf

                                                                T. Knieper, Bachelor's thesis, Paderborn University, 2008

                                                                @book{Knieper_2008, title={Implementierung und Bewertung des multikriteriellen Optimierungsverfahrens IBEA für den automatisierten Schaltungsentwurf}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2008} }


                                                                  Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme

                                                                  J. Niklas, Bachelor's thesis, Paderborn University, 2008

                                                                  @book{Niklas_2008, title={Eine Monitoring- und Debugging-Infrastruktur für hybride HW/SW-Systeme}, publisher={Paderborn University}, author={Niklas, Jörg}, year={2008} }


                                                                    Raytracing on a Custom Instruction Set CPU

                                                                    M. Östermann, Bachelor's thesis, Paderborn University, 2008

                                                                    @book{Östermann_2008, title={Raytracing on a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Östermann, Marco}, year={2008} }


                                                                      Design and Evaluation of MicroBlaze Multi-core Architectures

                                                                      N. Westerheide, Bachelor's thesis, Paderborn University, 2008

                                                                      @book{Westerheide_2008, title={Design and Evaluation of MicroBlaze Multi-core Architectures}, publisher={Paderborn University}, author={Westerheide, Nico}, year={2008} }


                                                                        VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen

                                                                        R. Meiche, Bachelor's thesis, Paderborn University, 2007

                                                                        @book{Meiche_2007, title={VHDL-Implementierung eines Clustering-Verfahrens für multikriterielle Optimierungsalgorithmen}, publisher={Paderborn University}, author={Meiche, Robert}, year={2007} }


                                                                          Distributed Simulation of mobile Robots using EyeSim

                                                                          T. Ceylan, C. Yalcin, Bachelor's thesis, Paderborn University, 2007

                                                                          @book{Ceylan_Yalcin_2007, title={Distributed Simulation of mobile Robots using EyeSim}, publisher={Paderborn University}, author={Ceylan, Toni and Yalcin, Coni}, year={2007} }


                                                                            FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks

                                                                            R. Mühlenbernd, Bachelor's thesis, Paderborn University, 2006

                                                                            @book{Mühlenbernd_2006, title={FPGA-Implementierung eines server-basierten Schedulers für periodische Hardwaretasks}, publisher={Paderborn University}, author={Mühlenbernd, Roland}, year={2006} }


                                                                              Open list in Research Information System

                                                                              Master's Theses


                                                                              Open list in Research Information System

                                                                              A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking

                                                                              M. Keerthipati, Master's thesis, Universität Paderborn, 2019

                                                                              Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis.

                                                                              @book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati, Monica}, year={2019} }


                                                                                Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers

                                                                                T. Hansmeier, Master's thesis, Universität Paderborn, 2019

                                                                                @book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }


                                                                                  Implementing a Real-time System on a Platform FPGA operated with ReconOS

                                                                                  C. Lienen, Master's thesis, Universität Paderborn, 2019

                                                                                  @book{Lienen_2019, title={Implementing a Real-time System on a Platform FPGA operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}, year={2019} }


                                                                                    Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip

                                                                                    J. Mehta, Master's thesis, 2019

                                                                                    @book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip}, author={Mehta, Jinay}, year={2019} }


                                                                                      Incremental learning with Support Vector Machine on embedded platforms

                                                                                      S. Kumar Jeyakumar, Master's thesis, 2019

                                                                                      @book{Kumar Jeyakumar_2019, title={Incremental learning with Support Vector Machine on embedded platforms}, author={Kumar Jeyakumar, Shankar}, year={2019} }


                                                                                        FPGA Acceleration of String Search Techniques in Huge Data Sets

                                                                                        N.S. Sabu, Master's thesis, Paderborn University, 2019

                                                                                        @book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019} }


                                                                                          Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data

                                                                                          L. Clausing, Master's thesis, Ruhr-University Bochum, 2018

                                                                                          @book{Clausing_2018, title={Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data}, publisher={Ruhr-University Bochum}, author={Clausing, Lennart}, year={2018} }


                                                                                            A Framework for the Synthesis of Approximate Circuits

                                                                                            L.M. Witschen, Master's thesis, Universität Paderborn, 2017

                                                                                            @book{Witschen_2017, title={A Framework for the Synthesis of Approximate Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias}, year={2017} }


                                                                                              Acceleration of Industrial Analytics Functions on a Platform FPGA

                                                                                              U. Riaz, Master's thesis, Paderborn University, 2017

                                                                                              @book{Riaz_2017, title={Acceleration of Industrial Analytics Functions on a Platform FPGA}, publisher={Paderborn University}, author={Riaz, Umair}, year={2017} }


                                                                                                Reconfigurable Cryptographic Services

                                                                                                A. Dietrich, Master's thesis, Paderborn University, 2017

                                                                                                @book{Dietrich_2017, title={Reconfigurable Cryptographic Services}, publisher={Paderborn University}, author={Dietrich, Andreas}, year={2017} }


                                                                                                  OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten

                                                                                                  C. Knorr, Master's thesis, Universität Paderborn, 2017

                                                                                                  @book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017} }


                                                                                                    Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion

                                                                                                    J. Cedric Mertens, Master's thesis, Paderborn University, 2016

                                                                                                    @book{Cedric Mertens_2016, title={Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion}, publisher={Paderborn University}, author={Cedric Mertens, Jan}, year={2016} }


                                                                                                      Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method

                                                                                                      O. Amin, Master's thesis, Paderborn University, 2016

                                                                                                      @book{Amin_2016, title={Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method}, publisher={Paderborn University}, author={Amin, Omair}, year={2016} }


                                                                                                        Implementation of Bilinear Pairings on Reconfigurable Hardware

                                                                                                        A.S. Nassery, Master's thesis, Paderborn University, 2016

                                                                                                        @book{Nassery_2016, title={Implementation of Bilinear Pairings on Reconfigurable Hardware}, publisher={Paderborn University}, author={Nassery, Abdul Sami}, year={2016} }


                                                                                                          Operating System Support for Reconfigurable Cache

                                                                                                          V. Makeswaran, Master's thesis, Paderborn University, 2016

                                                                                                          @book{Makeswaran_2016, title={Operating System Support for Reconfigurable Cache}, publisher={Paderborn University}, author={Makeswaran, Vignesh}, year={2016} }


                                                                                                            Private/Shared Data Classification and Implementation for a Multi-Softcore Platform

                                                                                                            I. Ibne Ashraf, Master's thesis, Paderborn University, 2016

                                                                                                            @book{Ibne Ashraf_2016, title={Private/Shared Data Classification and Implementation for a Multi-Softcore Platform}, publisher={Paderborn University}, author={Ibne Ashraf, Ishraq}, year={2016} }


                                                                                                              Self-Optimizing Organic Cache

                                                                                                              A.F. Ahmed, Master's thesis, Paderborn University, 2015

                                                                                                              @book{Ahmed_2015, title={Self-Optimizing Organic Cache}, publisher={Paderborn University}, author={Ahmed, Abdullah Fathi}, year={2015} }


                                                                                                                Evolution of Heat Flow Prediction Models for FPGA Devices

                                                                                                                H. Hangmann, Master's thesis, Paderborn University, 2015

                                                                                                                @book{Hangmann_2015, title={Evolution of Heat Flow Prediction Models for FPGA Devices}, publisher={Paderborn University}, author={Hangmann, Hendrik}, year={2015} }


                                                                                                                  Computer Vision basierte Klassifikation von HD EMG Signalen

                                                                                                                  C. Haupt, Master's thesis, Paderborn University, 2015

                                                                                                                  @book{Haupt_2015, title={Computer Vision basierte Klassifikation von HD EMG Signalen}, publisher={Paderborn University}, author={Haupt, Christian}, year={2015} }


                                                                                                                    Acceleration of Artificial Neural Networks on a Zynq Platform

                                                                                                                    T. Posewsky, Master's thesis, Paderborn University, 2015

                                                                                                                    @book{Posewsky_2015, title={Acceleration of Artificial Neural Networks on a Zynq Platform}, publisher={Paderborn University}, author={Posewsky, Thorbjörn}, year={2015} }


                                                                                                                      Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA

                                                                                                                      B. Koch, Master's thesis, Paderborn University, 2014

                                                                                                                      @book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin}, year={2014} }


                                                                                                                        A Generalized Loop Accelerator Implemented as a Coarse-Grained Array

                                                                                                                        M. Brand, Master's thesis, Paderborn University, 2014

                                                                                                                        @book{Brand_2014, title={A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel}, year={2014} }


                                                                                                                          Easy-to-use-on-the-fly binary program acceleration on many-cores

                                                                                                                          M. Damschen, Master's thesis, Paderborn University, 2014

                                                                                                                          @book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014} }


                                                                                                                            Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs

                                                                                                                            R. Mittendorf, Master's thesis, Paderborn University, 2014

                                                                                                                            @book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }


                                                                                                                              Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA

                                                                                                                              S. Surmund, Master's thesis, Paderborn University, 2014

                                                                                                                              @book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }


                                                                                                                                Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs

                                                                                                                                H. Riebler, Master's thesis, Paderborn University, 2013

                                                                                                                                @book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Paderborn University}, author={Riebler, Heinrich}, year={2013} }


                                                                                                                                  Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer

                                                                                                                                  D. Dridger, Master's thesis, Paderborn University, 2012

                                                                                                                                  @book{Dridger_2012, title={Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer}, publisher={Paderborn University}, author={Dridger, Denis}, year={2012} }


                                                                                                                                    Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go

                                                                                                                                    T. Graf, Master's thesis, Paderborn University, 2012

                                                                                                                                    @book{Graf_2012, title={Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go}, publisher={Paderborn University}, author={Graf, Tobias}, year={2012} }


                                                                                                                                      Analysis of Pattern Based Model Design and Learning in Computer-Go

                                                                                                                                      M. Wistuba, Master's thesis, Paderborn University, 2012

                                                                                                                                      @book{Wistuba_2012, title={Analysis of Pattern Based Model Design and Learning in Computer-Go}, publisher={Paderborn University}, author={Wistuba, Martin}, year={2012} }


                                                                                                                                        Analysis of Algorithmic Approaches for Temporal Partitioning

                                                                                                                                        A. Schwabe, Master's thesis, Paderborn University, 2011

                                                                                                                                        @book{Schwabe_2011, title={Analysis of Algorithmic Approaches for Temporal Partitioning}, publisher={Paderborn University}, author={Schwabe, Arne}, year={2011} }


                                                                                                                                          User Space Scheduling for Heterogeneous Systems

                                                                                                                                          D. Welp, Master's thesis, Paderborn University, 2011

                                                                                                                                          @book{Welp_2011, title={User Space Scheduling for Heterogeneous Systems}, publisher={Paderborn University}, author={Welp, Daniel}, year={2011} }


                                                                                                                                            Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen

                                                                                                                                            A. Agne, Master's thesis, Paderborn University, 2010

                                                                                                                                            @book{Agne_2010, title={Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen}, publisher={Paderborn University}, author={Agne, Andreas}, year={2010} }


                                                                                                                                              EMG-basierte Ganganalyse

                                                                                                                                              A. Boschmann, Master's thesis, Paderborn University, 2010

                                                                                                                                              @book{Boschmann_2010, title={EMG-basierte Ganganalyse}, publisher={Paderborn University}, author={Boschmann, Alexander}, year={2010} }


                                                                                                                                                Evolvable Cache Controller

                                                                                                                                                D. Breitlauch, Master's thesis, Paderborn University, 2010

                                                                                                                                                @book{Breitlauch_2010, title={Evolvable Cache Controller}, publisher={Paderborn University}, author={Breitlauch, Daniel}, year={2010} }


                                                                                                                                                  Hybridization of Global Multi-Objective and Local Search Techniques

                                                                                                                                                  T. Knieper, Master's thesis, Paderborn University, 2010

                                                                                                                                                  @book{Knieper_2010, title={Hybridization of Global Multi-Objective and Local Search Techniques}, publisher={Paderborn University}, author={Knieper, Tobias}, year={2010} }


                                                                                                                                                    FPGA/CPU Multicore-Plattform für ReconOS/eCos

                                                                                                                                                    R. Meiche, Master's thesis, Paderborn University, 2010

                                                                                                                                                    @book{Meiche_2010, title={FPGA/CPU Multicore-Plattform für ReconOS/eCos}, publisher={Paderborn University}, author={Meiche, Robert}, year={2010} }


                                                                                                                                                      Transparente Hardwarebeschleunigung durch Shared Library Interposing

                                                                                                                                                      M. Niekamp, Master's thesis, Paderborn University, 2010

                                                                                                                                                      @book{Niekamp_2010, title={Transparente Hardwarebeschleunigung durch Shared Library Interposing}, publisher={Paderborn University}, author={Niekamp, Manuel}, year={2010} }


                                                                                                                                                        A Token-Ring Network-On-Chip for Message Passing in ReconOS

                                                                                                                                                        B. Runde, Master's thesis, Paderborn University, 2010

                                                                                                                                                        @book{Runde_2010, title={A Token-Ring Network-On-Chip for Message Passing in ReconOS}, publisher={Paderborn University}, author={Runde, Bodo}, year={2010} }


                                                                                                                                                          Scheduling Support for Heterogeneous Hardware Accelerators under Linux

                                                                                                                                                          T. Wiersema, Master's thesis, Paderborn University, 2010

                                                                                                                                                          @book{Wiersema_2010, title={Scheduling Support for Heterogeneous Hardware Accelerators under Linux}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2010} }


                                                                                                                                                            Evolvable Robot Controller

                                                                                                                                                            A. Kostin, Master's thesis, Paderborn University, 2009

                                                                                                                                                            @book{Kostin_2009, title={Evolvable Robot Controller}, publisher={Paderborn University}, author={Kostin, Alexander}, year={2009} }


                                                                                                                                                              Compiler for a Custom Instruction Set CPU

                                                                                                                                                              M. Tofall, Master's thesis, Paderborn University, 2009

                                                                                                                                                              @book{Tofall_2009, title={Compiler for a Custom Instruction Set CPU}, publisher={Paderborn University}, author={Tofall, Martin}, year={2009} }


                                                                                                                                                                Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units

                                                                                                                                                                A. Warkentin, Master's thesis, Paderborn University, 2009

                                                                                                                                                                @book{Warkentin_2009, title={Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units}, publisher={Paderborn University}, author={Warkentin, Alexander}, year={2009} }


                                                                                                                                                                  Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern

                                                                                                                                                                  M. Happe, Master's thesis, Paderborn University, 2008

                                                                                                                                                                  @book{Happe_2008, title={Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern}, publisher={Paderborn University}, author={Happe, Markus}, year={2008} }


                                                                                                                                                                    Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen

                                                                                                                                                                    T. Beisel, Master's thesis, Paderborn University, 2007

                                                                                                                                                                    @book{Beisel_2007, title={Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen}, publisher={Paderborn University}, author={Beisel, Tobias}, year={2007} }


                                                                                                                                                                      Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme

                                                                                                                                                                      S. Döhre, Master's thesis, Paderborn University, 2007

                                                                                                                                                                      @book{Döhre_2007, title={Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme}, publisher={Paderborn University}, author={Döhre, Sven}, year={2007} }


                                                                                                                                                                        A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization

                                                                                                                                                                        B. Defo, Master's thesis, Paderborn University, 2007

                                                                                                                                                                        @book{Defo_2007, title={A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization}, publisher={Paderborn University}, author={Defo, Bertrand}, year={2007} }


                                                                                                                                                                          Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS

                                                                                                                                                                          W. Reisch, Master's thesis, Paderborn University, 2007

                                                                                                                                                                          @book{Reisch_2007, title={Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS}, publisher={Paderborn University}, author={Reisch, Waldemar}, year={2007} }


                                                                                                                                                                            Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem

                                                                                                                                                                            E. Rethmeier, Master's thesis, Paderborn University, 2007

                                                                                                                                                                            @book{Rethmeier_2007, title={Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem}, publisher={Paderborn University}, author={Rethmeier, Eike}, year={2007} }


                                                                                                                                                                              Open list in Research Information System

                                                                                                                                                                              Dissertations


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                                                                                                                                                                              FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization

                                                                                                                                                                              N. Ho, Universität Paderborn, 2018

                                                                                                                                                                              Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.

                                                                                                                                                                              @book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }


                                                                                                                                                                                Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing

                                                                                                                                                                                T. Beisel, Logos Verlag Berlin GmbH, 2015

                                                                                                                                                                                The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.

                                                                                                                                                                                @book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }


                                                                                                                                                                                  Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go

                                                                                                                                                                                  L. Schäfers, Logos Verlag Berlin GmbH, 2014

                                                                                                                                                                                  Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.

                                                                                                                                                                                  @book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }


                                                                                                                                                                                    Performance and thermal management on self-adaptive hybrid multi-cores

                                                                                                                                                                                    M. Happe, Logos Verlag Berlin GmbH, 2013

                                                                                                                                                                                    Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time.

                                                                                                                                                                                    @book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }


                                                                                                                                                                                    Adapting Hardware Systems by Means of Multi-Objective Evolution

                                                                                                                                                                                    P. Kaufmann, Logos Verlag Berlin GmbH, 2013

                                                                                                                                                                                    Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.

                                                                                                                                                                                    @book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }


                                                                                                                                                                                      Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security

                                                                                                                                                                                      S. Drzevitzky, Universität Paderborn, 2012

                                                                                                                                                                                      FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.

                                                                                                                                                                                      @book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }


                                                                                                                                                                                      Design and Programming of Reconfigurable Mesh based Many-Cores

                                                                                                                                                                                      H. Giefers, Logos Verlag Berlin GmbH, 2012

                                                                                                                                                                                      The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores. The book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.

                                                                                                                                                                                      @book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }


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