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FBench: Defining and Optimizing OpenCL Benchmarks for FPGAs

Term WS 2019/20 + SS 2020
Program Computer Science Master's
Computer Engineering Master's
Lecture number L.079.07027

11 Students assigned by central distribution, possibly 1 space free for redistribution
Kickoff Meeting on Friday October 11, 9:15 in room 2.267

Regular Meeting Hours Friday 9-14
Second time slot on agreement

Goals and Contents

Benchmarks are an important tool to characterize computer systems, compare them to other systems and identify strenghts and weaknesses. For CPUs and partially for GPUs, a variaty of benchmarks exists on various levels of abstraction, from pure microbenchmarks over simple kernels taken out of real world applications, up to the full application with realistic input data sets. With FPGAs emerging as an important accelerator technology for datacenter and HPC, a few of those benchmarks have been functionally ported to FPGAs using OpenCL. However, they lack a systematic coverage of FPGAs' architectural features. This project will aim on filling that gap with a focus simple, but meaningfull and well understood benchmark kernels.

In this project, you will get familiar with FPGA programming using OpenCL and develop a benchmark suite for FPGA with the following features and properties

  • Simple, synthetic benchmarks to cover relevant performance metrics
    • Global memory bandwidth with different access patterns
    • Local memory bandwidth with different data partitions
    • Operations (floating point, integer, logic) using DSPs and LUTs
    • Internal communication on chip, routing limits
    • External communication to other FPGAs
  • Benchmark suite that is easy to use
    • Clone repository, type make, get score + explanation
    • Straight forward OpenCL code + documentation
  • Optimized benchmark versions for some FPGAs
    • Special variants to perform better than the simple code
  • Provide parameters for scaling
    • Peak operations / local memory requires usage of all (~90%) resources

Next steps

The further project organization will be performed in gitlab at

Email instructions on how to get access have been sent.

Participant Background

For the assignment phase, we have prepared a set of questions on your personal experience and study background in the topics relevant for this project and a set of technical questions. The questions on your background include the following aspects

  • What is your background knowledge or practical experience in
    • Accelerator programming (OpenCL, CUDA, other) or other programming projects
    • FPGA architecture and tools
    • Benchmarking and performance metrics
    • Project management
    • Agile development and continuous integration
    • Git version control and handling of open source projects
    • Linux command line, ssh and scripting
  • Which of the following lectures have you attended or successfully passed
    • Reconfigurable Computing
    • High-Performance Computing
    • Architektur Paralleler Rechnersysteme
    • Advanced Computer Architecture

The technical questions have been released on August 10. Please submit all answers in the Jupyter evaluation tool at starting August 10. By mistake, the first released assignment form states that we plan for personal interviews. This is not the case, the ranking will be done only based on the submitted answers. If you have fetched the assignment form prior to August 20, you will still see this wrong introduction. The questions in the form are unchanged, so all submissions will work.

Note: the technical resources below will be relevant material for the project itself, but the questions asked in the assignment phase will not build upon this material. The questions will rather ask for broader technical background around Linux and ssh usage, benchmarks and performance models, and accelerator programming strategies.


Previous Steps

  • Project presented on July 8.
  • Assignments published on August 10.
  • Assignment form fixed on August 20 - no personal interviews planned.
  • Group allocation according to stable marriage process completed on October 2.
Supervisor Team

Dr. Tobias Kenter


+49 5251 60-4340
+49 5251 60-1714

Prof. Dr. Christian Plessl


Christian Plessl
+49 5251 60-5399
+49 5251 60-1714

Marius Meyer


Marius Meyer
+49 5251 60-1718
+49 5251 60-1714

Die Universität der Informationsgesellschaft