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Team

Felix Jentzsch, M.Sc.

Kontakt
 Felix Jentzsch, M.Sc.

Technische Informatik

Mitglied - Wissenschaftlicher Mitarbeiter

Telefon:
+49 5251 60-5395
Büro:
O3.122
Web:
Besucher:
Pohlweg 51
33098 Paderborn

Publications


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Konferenzbeiträge

FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics

H.. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R.. Arshad, S. Rautmare, S. Manjunatha, M. Platzner, A. Boschmann, D.. Schollbach, in: Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021

@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021, title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}, booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}, author={Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }, year={2021} }


Zeitschriftenaufsätze

RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures

F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro (2022), 42(6), pp. 125-133

Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.

@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={10.1109/MM.2022.3202091}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }


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Die Universität der Informationsgesellschaft